From 5170b71143d99a650921cb87223a0b3f46a74fb4 Mon Sep 17 00:00:00 2001 From: Shih-wei Liao Date: Wed, 26 May 2010 00:02:28 +0000 Subject: [PATCH] To handle s* registers in emitVFPLoadStoreMultipleInstruction(). Fixing http://llvm.org/bugs/show_bug.cgi?id=7221. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104652 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMCodeEmitter.cpp | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp index 210022911b2..eaf47607171 100644 --- a/lib/Target/ARM/ARMCodeEmitter.cpp +++ b/lib/Target/ARM/ARMCodeEmitter.cpp @@ -146,11 +146,11 @@ namespace { return getMachineOpValue(MI, MI.getOperand(OpIdx)); } - /// getMovi32Value - Return binary encoding of operand for movw/movt. If the + /// getMovi32Value - Return binary encoding of operand for movw/movt. If the /// machine operand requires relocation, record the relocation and return zero. - unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO, + unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO, unsigned Reloc); - unsigned getMovi32Value(const MachineInstr &MI, unsigned OpIdx, + unsigned getMovi32Value(const MachineInstr &MI, unsigned OpIdx, unsigned Reloc) { return getMovi32Value(MI, MI.getOperand(OpIdx), Reloc); } @@ -227,12 +227,12 @@ unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const { return 0; } -/// getMovi32Value - Return binary encoding of operand for movw/movt. If the +/// getMovi32Value - Return binary encoding of operand for movw/movt. If the /// machine operand requires relocation, record the relocation and return zero. unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI, - const MachineOperand &MO, + const MachineOperand &MO, unsigned Reloc) { - assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw)) + assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw)) && "Relocation to this function should be for movt or movw"); if (MO.isImm()) @@ -1459,7 +1459,12 @@ ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) { break; ++NumRegs; } - Binary |= NumRegs * 2; + // Bit 8 will be set if is consecutive 64-bit registers (e.g., D0) + // Otherwise, it will be 0, in the case of 32-bit registers. + if(Binary & 0x100) + Binary |= NumRegs * 2; + else + Binary |= NumRegs; emitWordLE(Binary); }