6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-13 04:30:23 +00:00
Code Issues Projects Releases Wiki Activity

X86: Fix type check. Just because an integer type is illegal doesn't mean it's i64.

Browse Source 
Fixes PR17495, where an i24 triggered this code. It's intended to
optimize i64 loads on 32 bit x86.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192123 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Benjamin Kramer 2013-10-07 19:11:35 +00:00
parent 96ba8cb9b2
commit 51a8280fbb
2 changed files with 19 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/X86/X86ISelLowering.cpp
View File

@ -18823,7 +18823,7 @@ static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
!XTLI->getSubtarget()->is64Bit() &&
!DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
VT == MVT::i64) {
SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
Ld->getChain(), Op0, DAG);
DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));

18
test/CodeGen/X86/2011-06-03-x87chain.ll
View File

@ -29,3 +29,21 @@ entry:
store float %conv, float* %f, align 4
ret float %conv
}
define void @PR17495() {
entry:
br i1 undef, label %while.end, label %while.body
while.body: ; preds = %while.body, %entry
%x.1.copyload = load i24* undef, align 1
%conv = sitofp i24 %x.1.copyload to float
%div = fmul float %conv, 0x3E80000000000000
store float %div, float* undef, align 4
br i1 false, label %while.end, label %while.body
while.end: ; preds = %while.body, %entry
ret void
; CHECK-LABEL: @PR17495
; CHECK-NOT: fildll
}