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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-18 12:29:21 +00:00
* Cleaned up addressing mode matching code.
* Cleaned up and tweaked LEA cost analysis code. Removed some hacks. * Handle ADD $X, c to MOV32ri $X+c. These patterns cannot be autogen'd and they need to be matched before LEA. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26376 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -46,7 +46,6 @@ namespace {
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enum {
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RegBase,
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FrameIndexBase,
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ConstantPoolBase
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} BaseType;
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struct { // This is really a union, discriminated by BaseType!
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@ -58,9 +57,12 @@ namespace {
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SDOperand IndexReg;
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unsigned Disp;
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GlobalValue *GV;
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Constant *CP;
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unsigned Align; // CP alignment.
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X86ISelAddressMode()
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: BaseType(RegBase), Scale(1), IndexReg(), Disp(0), GV(0) {
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: BaseType(RegBase), Scale(1), IndexReg(), Disp(0), GV(0),
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CP(0), Align(0) {
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}
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};
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}
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@ -132,7 +134,9 @@ namespace {
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Scale = getI8Imm(AM.Scale);
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Index = AM.IndexReg;
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Disp = AM.GV ? CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp)
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: getI32Imm(AM.Disp);
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: (AM.CP ?
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CurDAG->getTargetConstantPool(AM.CP, MVT::i32, AM.Align, AM.Disp)
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: getI32Imm(AM.Disp));
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}
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/// getI8Imm - Return a target constant with the specified value, of type
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@ -266,26 +270,44 @@ void X86DAGToDAGISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
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/// addressing mode
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bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
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bool isRoot) {
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bool StopHere = false;
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// If N has already been selected, we may or may not want to fold its
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// operands into the addressing mode. It will result in code duplication!
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// FIXME: Right now we do. That is, as long as the selected target node
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// does not produce a chain. This may require a more sophisticated heuristics.
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bool Available = false;
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// If N has already been selected, reuse the result unless in some very
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// specific cases.
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std::map<SDOperand, SDOperand>::iterator CGMI= CodeGenMap.find(N.getValue(0));
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if (CGMI != CodeGenMap.end()) {
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if (isRoot)
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// Stop here if it is a root. It's probably not profitable to go deeper.
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StopHere = true;
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else {
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for (unsigned i = 0, e = CGMI->second.Val->getNumValues(); i != e; ++i) {
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if (CGMI->second.Val->getValueType(i) == MVT::Other)
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StopHere = true;
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}
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}
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Available = true;
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}
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switch (N.getOpcode()) {
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default: break;
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case ISD::Constant:
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AM.Disp += cast<ConstantSDNode>(N)->getValue();
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return false;
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case X86ISD::Wrapper:
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// If both base and index components have been picked, we can't fit
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// the result available in the register in the addressing mode. Duplicate
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// GlobalAddress or ConstantPool as displacement.
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if (!Available || (AM.Base.Reg.Val && AM.IndexReg.Val)) {
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if (ConstantPoolSDNode *CP =
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dyn_cast<ConstantPoolSDNode>(N.getOperand(0))) {
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if (AM.CP == 0) {
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AM.CP = CP->get();
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AM.Align = CP->getAlignment();
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AM.Disp += CP->getOffset();
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return false;
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}
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} else if (GlobalAddressSDNode *G =
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dyn_cast<GlobalAddressSDNode>(N.getOperand(0))) {
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if (AM.GV == 0) {
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AM.GV = G->getGlobal();
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AM.Disp += G->getOffset();
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return false;
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}
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}
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}
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break;
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case ISD::FrameIndex:
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if (AM.BaseType == X86ISelAddressMode::RegBase && AM.Base.Reg.Val == 0) {
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AM.BaseType = X86ISelAddressMode::FrameIndexBase;
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@ -294,48 +316,8 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
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}
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break;
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case ISD::ConstantPool:
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if (AM.BaseType == X86ISelAddressMode::RegBase && AM.Base.Reg.Val == 0) {
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if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N)) {
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AM.BaseType = X86ISelAddressMode::ConstantPoolBase;
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AM.Base.Reg = CurDAG->getTargetConstantPool(CP->get(), MVT::i32,
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CP->getAlignment());
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return false;
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}
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}
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break;
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case ISD::GlobalAddress:
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if (AM.GV == 0) {
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AM.GV = cast<GlobalAddressSDNode>(N)->getGlobal();
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return false;
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}
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break;
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case X86ISD::Wrapper:
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if (ConstantPoolSDNode *CP =
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dyn_cast<ConstantPoolSDNode>(N.getOperand(0))) {
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if (AM.BaseType == X86ISelAddressMode::RegBase && AM.Base.Reg.Val == 0) {
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AM.BaseType = X86ISelAddressMode::ConstantPoolBase;
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AM.Base.Reg = CurDAG->getTargetConstantPool(CP->get(), MVT::i32,
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CP->getAlignment());
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return false;
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}
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} else if (GlobalAddressSDNode *G =
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dyn_cast<GlobalAddressSDNode>(N.getOperand(0))) {
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if (AM.GV == 0) {
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AM.GV = cast<GlobalAddressSDNode>(N.getOperand(0))->getGlobal();
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return false;
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}
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}
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break;
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case ISD::Constant:
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AM.Disp += cast<ConstantSDNode>(N)->getValue();
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return false;
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case ISD::SHL:
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if (!StopHere && AM.IndexReg.Val == 0 && AM.Scale == 1)
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if (!Available && AM.IndexReg.Val == 0 && AM.Scale == 1)
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1))) {
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unsigned Val = CN->getValue();
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if (Val == 1 || Val == 2 || Val == 3) {
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@ -361,8 +343,10 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
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case ISD::MUL:
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// X*[3,5,9] -> X+X*[2,4,8]
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if (!StopHere && AM.IndexReg.Val == 0 && AM.BaseType == X86ISelAddressMode::RegBase &&
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AM.Base.Reg.Val == 0)
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if (!Available &&
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AM.BaseType == X86ISelAddressMode::RegBase &&
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AM.Base.Reg.Val == 0 &&
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AM.IndexReg.Val == 0)
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1)))
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if (CN->getValue() == 3 || CN->getValue() == 5 || CN->getValue() == 9) {
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AM.Scale = unsigned(CN->getValue())-1;
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@ -389,7 +373,7 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
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break;
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case ISD::ADD: {
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if (!StopHere) {
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if (!Available) {
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X86ISelAddressMode Backup = AM;
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if (!MatchAddress(N.Val->getOperand(0), AM, false) &&
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!MatchAddress(N.Val->getOperand(1), AM, false))
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@ -406,10 +390,6 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
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// Is the base register already occupied?
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if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base.Reg.Val) {
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// TargetConstantPool cannot be anything but the base.
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if (N.getOpcode() == ISD::TargetConstantPool)
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return true;
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// If so, check to see if the scale index register is set.
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if (AM.IndexReg.Val == 0) {
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AM.IndexReg = N;
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@ -445,9 +425,56 @@ bool X86DAGToDAGISel::SelectAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
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AM.IndexReg = CurDAG->getRegister(0, MVT::i32);
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getAddressOperands(AM, Base, Scale, Index, Disp);
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return true;
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}
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/// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
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/// mode it matches can be cost effectively emitted as an LEA instruction.
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/// For X86, it always is unless it's just a (Reg + const).
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bool X86DAGToDAGISel::SelectLEAAddr(SDOperand N, SDOperand &Base,
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SDOperand &Scale,
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SDOperand &Index, SDOperand &Disp) {
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X86ISelAddressMode AM;
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if (MatchAddress(N, AM))
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return false;
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unsigned Complexity = 0;
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if (AM.BaseType == X86ISelAddressMode::RegBase)
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if (AM.Base.Reg.Val)
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Complexity = 1;
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else
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AM.Base.Reg = CurDAG->getRegister(0, MVT::i32);
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else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
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Complexity = 4;
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if (AM.IndexReg.Val)
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Complexity++;
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else
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AM.IndexReg = CurDAG->getRegister(0, MVT::i32);
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if (AM.Scale > 1)
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Complexity += 2;
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// FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
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// to a LEA. This is determined with some expermentation but is by no means
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// optimal (especially for code size consideration). LEA is nice because of
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// its three-address nature. Tweak the cost function again when we can run
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// convertToThreeAddress() at register allocation time.
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if (AM.GV || AM.CP)
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Complexity += 2;
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if (AM.Disp && (AM.Base.Reg.Val || AM.IndexReg.Val))
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Complexity++;
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if (Complexity > 2) {
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getAddressOperands(AM, Base, Scale, Index, Disp);
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return true;
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}
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return false;
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}
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bool X86DAGToDAGISel::TryFoldLoad(SDOperand P, SDOperand N,
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SDOperand &Base, SDOperand &Scale,
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SDOperand &Index, SDOperand &Disp) {
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@ -465,67 +492,6 @@ static bool isRegister0(SDOperand Op) {
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return false;
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}
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/// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
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/// mode it matches can be cost effectively emitted as an LEA instruction.
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/// For X86, it always is unless it's just a (Reg + const).
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bool X86DAGToDAGISel::SelectLEAAddr(SDOperand N, SDOperand &Base,
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SDOperand &Scale,
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SDOperand &Index, SDOperand &Disp) {
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X86ISelAddressMode AM;
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if (!MatchAddress(N, AM)) {
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bool SelectIndex = false;
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bool Check = false;
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if (AM.BaseType == X86ISelAddressMode::RegBase) {
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if (AM.Base.Reg.Val)
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Check = true;
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else
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AM.Base.Reg = CurDAG->getRegister(0, MVT::i32);
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}
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if (AM.IndexReg.Val)
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SelectIndex = true;
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else
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AM.IndexReg = CurDAG->getRegister(0, MVT::i32);
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if (Check) {
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unsigned Complexity = 0;
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if (AM.Scale > 1)
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Complexity++;
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if (SelectIndex)
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Complexity++;
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if (AM.GV) {
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Complexity++;
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if (AM.Disp)
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Complexity++;
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} else if (AM.Disp > 1)
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Complexity++;
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// Suppose base == %eax and it has multiple uses, then instead of
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// movl %eax, %ecx
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// addl $8, %ecx
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// use
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// leal 8(%eax), %ecx.
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// FIXME: If the other uses ended up being scheduled ahead of the leal
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// then it would have been better to use the addl. The proper way to
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// handle this is with using X86InstrInfo::convertToThreeAddress hook.
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// From an email:
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// BTW, this problem is the one that inspired the
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// "X86InstrInfo::convertToThreeAddress" hook (which would handle this
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// the "right" way). Unfortunately the X86 implementation of this is
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// disabled, because we don't currently have enough information handy to
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// know that the flags from the add is dead when the hook is called (from
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// the register allocator).
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if (AM.Base.Reg.Val->use_size() > 1)
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Complexity++;
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if (Complexity <= 1)
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return false;
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}
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getAddressOperands(AM, Base, Scale, Index, Disp);
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return true;
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}
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return false;
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}
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/// getGlobalBaseReg - Output the instructions required to put the
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/// base address to use for accessing globals into a register.
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///
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@ -589,38 +555,43 @@ void X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) {
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Result = getGlobalBaseReg();
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return;
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case X86ISD::Wrapper: {
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// It's beneficial to manully select the wrapper nodes here rather
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// then using tablgen'd code to match this. We do not want to mutate the
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// node to MOV32ri and we do not want to record this in CodeGenMap.
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// We want to allow the wrapped leaf nodes be duplicated so they can
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// be used in addressing modes.
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// e.g.
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// 0xa59e4a0: i32 = TargetGlobalAddress <xxx> 0
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// 0xa59e740: i32 = X86ISD::Wrapper 0xa59e4a0
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// ...
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// 0xa59e880: i32 = add 0xa59e740, 0xa59e800
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// ...
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// 0xa59e880: <multiple use>
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// 0xa59e970: i32 = add 0xa59e880, 0xa59e910
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// ...
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// 0xa59ea60: i32,ch = load 0xa589780, 0xa59e970, 0xa59ea00
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// ...
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// 0xa59e880: <multiple use>
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// 0xa59eb60: ch = CopyToReg 0xa59ea60:1, 0xa59eaf0, 0xa59e880
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// By allowing the TargetGlobalAddress to be duplicated, it can appear
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// in the load address as well as an operand of the add.
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Result = SDOperand(CurDAG->getTargetNode(X86::MOV32ri, MVT::i32,
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N.getOperand(0)), 0);
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#ifndef NDEBUG
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DEBUG(std::cerr << std::string(Indent-2, ' '));
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DEBUG(std::cerr << "== ");
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DEBUG(Result.Val->dump(CurDAG));
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DEBUG(std::cerr << "\n");
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Indent -= 2;
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#endif
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case ISD::ADD: {
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// Turn ADD X, c to MOV32ri X+c. This cannot be done with tblgen'd
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// code and is matched first so to prevent it from being turned into
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// LEA32r X+c.
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SDOperand N0 = N.getOperand(0);
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SDOperand N1 = N.getOperand(1);
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if (N.Val->getValueType(0) == MVT::i32 &&
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N0.getOpcode() == X86ISD::Wrapper &&
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N1.getOpcode() == ISD::Constant) {
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unsigned Offset = (unsigned)cast<ConstantSDNode>(N1)->getValue();
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SDOperand C(0, 0);
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// TODO: handle ExternalSymbolSDNode.
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if (GlobalAddressSDNode *G =
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dyn_cast<GlobalAddressSDNode>(N0.getOperand(0))) {
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C = CurDAG->getTargetGlobalAddress(G->getGlobal(), MVT::i32,
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G->getOffset() + Offset);
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} else if (ConstantPoolSDNode *CP =
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dyn_cast<ConstantPoolSDNode>(N0.getOperand(0))) {
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C = CurDAG->getTargetConstantPool(CP->get(), MVT::i32,
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CP->getAlignment(),
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CP->getOffset()+Offset);
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}
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if (C.Val) {
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if (N.Val->hasOneUse()) {
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Result = CurDAG->SelectNodeTo(N.Val, X86::MOV32ri, MVT::i32, C);
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} else {
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SDNode *ResNode = CurDAG->getTargetNode(X86::MOV32ri, MVT::i32, C);
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Result = CodeGenMap[N] = SDOperand(ResNode, 0);
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}
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return;
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}
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}
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// Other cases are handled by auto-generated code.
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break;
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}
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case ISD::MULHU:
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case ISD::MULHS: {
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