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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72604 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2009-05-30 01:09:53 +00:00
parent 4d4eab219a
commit 51b16f4737
16 changed files with 70 additions and 75 deletions
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8
lib/CodeGen/AsmPrinter/DwarfDebug.cpp
View File

@ -969,12 +969,6 @@ DbgScope *DwarfDebug::getOrCreateScope(GlobalVariable *V) {
DbgScope *Parent = NULL;
DIBlock Block(V);
// Don't create a new scope if we already created one for an inlined function.
DenseMap<const GlobalVariable *, DbgScope *>::iterator
II = AbstractInstanceRootMap.find(V);
if (II != AbstractInstanceRootMap.end())
return LexicalScopeStack.back();
if (!Block.isNull()) {
DIDescriptor ParentDesc = Block.getContext();
Parent =
@ -1030,6 +1024,8 @@ void DwarfDebug::ConstructDbgScope(DbgScope *ParentScope,
AddLabel(Die, dwarf::DW_AT_high_pc, dwarf::DW_FORM_addr,
DWLabel("func_end", SubprogramCount));
// Add the scope's contents.
ConstructDbgScope(ConcreteInst, StartID, EndID, Die, Unit);
ParentDie->AddChild(Die);
}

2
lib/CodeGen/RegAllocPBQP.cpp
View File

@ -729,7 +729,7 @@ void PBQPRegAlloc::finalizeAlloc() const {
// First allocate registers for the empty intervals.
for (LiveIntervalSet::const_iterator
itr = emptyVRegIntervals.begin(), end = emptyVRegIntervals.end();
itr = emptyVRegIntervals.begin(), end = emptyVRegIntervals.end();
itr != end; ++itr) {
LiveInterval *li = *itr;

8
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -5616,8 +5616,8 @@ void SDNode::printr(raw_ostream &OS, const SelectionDAG *G) const {
typedef SmallPtrSet<const SDNode *, 128> VisitedSDNodeSet;
static void DumpNodesr(raw_ostream &OS, const SDNode *N, unsigned indent,
const SelectionDAG *G, VisitedSDNodeSet &once) {
if (!once.insert(N)) // If we've been here before, return now.
const SelectionDAG *G, VisitedSDNodeSet &once) {
if (!once.insert(N)) // If we've been here before, return now.
return;
// Dump the current SDNode, but don't end the line yet.
OS << std::string(indent, ' ');
@ -5631,10 +5631,10 @@ static void DumpNodesr(raw_ostream &OS, const SDNode *N, unsigned indent,
// This child has no grandchildren; print it inline right here.
child->printr(OS, G);
once.insert(child);
} else { // Just the address. FIXME: also print the child's opcode
} else { // Just the address. FIXME: also print the child's opcode
OS << (void*)child;
if (unsigned RN = N->getOperand(i).getResNo())
OS << ":" << RN;
OS << ":" << RN;
}
}
OS << "\n";

2
lib/Support/ManagedStatic.cpp
View File

@ -42,7 +42,7 @@ void ManagedStaticBase::RegisterManagedStatic(void *(*Creator)(),
ManagedStaticMutex->release();
} else {
assert(Ptr == 0 && DeleterFn == 0 && Next == 0 &&
"Partially initialized ManagedStatic!?");
"Partially initialized ManagedStatic!?");
Ptr = Creator ? Creator() : 0;
DeleterFn = Deleter;

77
lib/System/Unix/Path.inc
View File

@ -271,52 +271,52 @@ static int
test_dir(char buf[PATH_MAX], char ret[PATH_MAX],
const char *dir, const char *bin)
{
struct stat sb;
struct stat sb;
snprintf(buf, PATH_MAX, "%s//%s", dir, bin);
if (realpath(buf, ret) == NULL)
return (1);
if (stat(buf, &sb) != 0)
return (1);
return (0);
snprintf(buf, PATH_MAX, "%s//%s", dir, bin);
if (realpath(buf, ret) == NULL)
return (1);
if (stat(buf, &sb) != 0)
return (1);
return (0);
}
static char *
getprogpath(char ret[PATH_MAX], const char *bin)
{
char *pv, *s, *t, buf[PATH_MAX];
char *pv, *s, *t, buf[PATH_MAX];
/* First approach: absolute path. */
if (bin[0] == '/') {
if (test_dir(buf, ret, "/", bin) == 0)
return (ret);
return (NULL);
}
/* First approach: absolute path. */
if (bin[0] == '/') {
if (test_dir(buf, ret, "/", bin) == 0)
return (ret);
return (NULL);
}
/* Second approach: relative path. */
if (strchr(bin, '/') != NULL) {
if (getcwd(buf, PATH_MAX) == NULL)
return (NULL);
if (test_dir(buf, ret, buf, bin) == 0)
return (ret);
return (NULL);
}
/* Second approach: relative path. */
if (strchr(bin, '/') != NULL) {
if (getcwd(buf, PATH_MAX) == NULL)
return (NULL);
if (test_dir(buf, ret, buf, bin) == 0)
return (ret);
return (NULL);
}
/* Third approach: $PATH */
if ((pv = getenv("PATH")) == NULL)
return (NULL);
s = pv = strdup(pv);
if (pv == NULL)
return (NULL);
while ((t = strsep(&s, ":")) != NULL) {
if (test_dir(buf, ret, t, bin) == 0) {
free(pv);
return (ret);
}
}
free(pv);
return (NULL);
/* Third approach: $PATH */
if ((pv = getenv("PATH")) == NULL)
return (NULL);
s = pv = strdup(pv);
if (pv == NULL)
return (NULL);
while ((t = strsep(&s, ":")) != NULL) {
if (test_dir(buf, ret, t, bin) == 0) {
free(pv);
return (ret);
}
}
free(pv);
return (NULL);
}
#endif
@ -341,7 +341,7 @@ Path Path::GetMainExecutable(const char *argv0, void *MainAddr) {
int err = dladdr(MainAddr, &DLInfo);
if (err == 0)
return Path();
// If the filename is a symlink, we need to resolve and return the location of
// the actual executable.
char link_path[MAXPATHLEN];
@ -874,4 +874,3 @@ void Path::UnMapFilePages(const char *BasePtr, uint64_t FileSize) {
}
} // end llvm namespace

2
lib/Target/ARM/ARMRegisterInfo.cpp
View File

@ -1522,7 +1522,7 @@ unsigned ARMRegisterInfo::getEHHandlerRegister() const {
}
int ARMRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
}
#include "ARMGenRegisterInfo.inc"

4
lib/Target/CellSPU/SPUISelDAGToDAG.cpp
View File

@ -872,12 +872,12 @@ SPUDAGToDAGISel::Select(SDValue Op) {
} else if (OpVT == MVT::v2f64) {
Opc = SPU::XORfnegvec;
signMask = emitBuildVector(CurDAG->getNode(ISD::BUILD_VECTOR, dl,
MVT::v2i64,
MVT::v2i64,
negConst, negConst));
}
return CurDAG->getTargetNode(Opc, dl, OpVT,
Op.getOperand(0), SDValue(signMask, 0));
Op.getOperand(0), SDValue(signMask, 0));
} else if (Opc == ISD::FABS) {
if (OpVT == MVT::f64) {
SDNode *signMask = SelectI64Constant(0x7fffffffffffffffULL, MVT::i64, dl);

2
lib/Target/PIC16/PIC16ISelLowering.cpp
View File

@ -535,7 +535,7 @@ void PIC16TargetLowering::GetExpandedParts(SDValue Op, SelectionDAG &DAG,
// Extract the lo component.
Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NewVT, Op,
DAG.getConstant(0, MVT::i8));
// extract the hi component
Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NewVT, Op,
DAG.getConstant(1, MVT::i8));

2
lib/Target/PIC16/PIC16ISelLowering.h
View File

@ -49,7 +49,7 @@ namespace llvm {
RRF, // Rotate right through carry
CALL, // PIC16 Call instruction
CALLW, // PIC16 CALLW instruction
SUBCC, // Compare for equality or inequality.
SUBCC, // Compare for equality or inequality.
SELECT_ICC, // Psuedo to be caught in schedular and expanded to brcond.
BRCOND, // Conditional branch.
Dummy

4
lib/Target/TargetRegisterInfo.cpp
View File

@ -23,9 +23,9 @@ using namespace llvm;
TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
regclass_iterator RCB, regclass_iterator RCE,
int CFSO, int CFDO,
const unsigned* subregs, const unsigned subregsize,
const unsigned* subregs, const unsigned subregsize,
const unsigned* superregs, const unsigned superregsize,
const unsigned* aliases, const unsigned aliasessize)
const unsigned* aliases, const unsigned aliasessize)
: SubregHash(subregs), SubregHashSize(subregsize),
SuperregHash(superregs), SuperregHashSize(superregsize),
AliasesHash(aliases), AliasesHashSize(aliasessize),

4
lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
View File

@ -451,7 +451,7 @@ void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
break;
case TLSModel::LocalDynamic:
// O << "@TLSLD"; // local dynamic not implemented
O << "@TLSGD";
O << "@TLSGD";
break;
case TLSModel::InitialExec:
if (Subtarget->is64Bit()) {
@ -465,7 +465,7 @@ void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
if (Subtarget->is64Bit())
O << "@TPOFF";
else
O << "@NTPOFF";
O << "@NTPOFF";
break;
default:
assert (0 && "Unknown TLS model");

12
lib/Target/X86/X86ISelLowering.cpp
View File

@ -6974,7 +6974,7 @@ X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
// Insert instructions into newMBB based on incoming instruction
assert(bInstr->getNumOperands() < X86AddrNumOperands + 4 &&
"unexpected number of operands");
"unexpected number of operands");
DebugLoc dl = bInstr->getDebugLoc();
MachineOperand& destOper = bInstr->getOperand(0);
MachineOperand* argOpers[2 + X86AddrNumOperands];
@ -7084,7 +7084,7 @@ X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
// Insert instructions into newMBB based on incoming instruction
// There are 8 "real" operands plus 9 implicit def/uses, ignored here.
assert(bInstr->getNumOperands() < X86AddrNumOperands + 14 &&
"unexpected number of operands");
"unexpected number of operands");
MachineOperand& dest1Oper = bInstr->getOperand(0);
MachineOperand& dest2Oper = bInstr->getOperand(1);
MachineOperand* argOpers[2 + X86AddrNumOperands];
@ -7131,7 +7131,7 @@ X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
int valArgIndx = lastAddrIndx + 1;
assert((argOpers[valArgIndx]->isReg() ||
argOpers[valArgIndx]->isImm()) &&
argOpers[valArgIndx]->isImm()) &&
"invalid operand");
unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
@ -7143,9 +7143,9 @@ X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
MIB.addReg(tt1);
(*MIB).addOperand(*argOpers[valArgIndx]);
assert(argOpers[valArgIndx + 1]->isReg() ==
argOpers[valArgIndx]->isReg());
argOpers[valArgIndx]->isReg());
assert(argOpers[valArgIndx + 1]->isImm() ==
argOpers[valArgIndx]->isImm());
argOpers[valArgIndx]->isImm());
if (argOpers[valArgIndx + 1]->isReg())
MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
else
@ -7226,7 +7226,7 @@ X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
DebugLoc dl = mInstr->getDebugLoc();
// Insert instructions into newMBB based on incoming instruction
assert(mInstr->getNumOperands() < X86AddrNumOperands + 4 &&
"unexpected number of operands");
"unexpected number of operands");
MachineOperand& destOper = mInstr->getOperand(0);
MachineOperand* argOpers[2 + X86AddrNumOperands];
int numArgs = mInstr->getNumOperands() - 1;

4
lib/Target/XCore/XCoreInstrInfo.cpp
View File

@ -431,8 +431,8 @@ void XCoreInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
}
bool XCoreInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI) const
MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI) const
{
if (CSI.empty()) {
return true;

2
lib/Target/XCore/XCoreInstrInfo.h
View File

@ -90,7 +90,7 @@ public:
SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const;
virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI) const;

10
lib/Target/XCore/XCoreInstrInfo.td
View File

@ -50,17 +50,17 @@ def SDT_XCoreAddress : SDTypeProfile<1, 1,
[SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
def pcrelwrapper : SDNode<"XCoreISD::PCRelativeWrapper", SDT_XCoreAddress,
[]>;
[]>;
def dprelwrapper : SDNode<"XCoreISD::DPRelativeWrapper", SDT_XCoreAddress,
[]>;
[]>;
def cprelwrapper : SDNode<"XCoreISD::CPRelativeWrapper", SDT_XCoreAddress,
[]>;
[]>;
def SDT_XCoreStwsp : SDTypeProfile<0, 2, [SDTCisInt<1>]>;
def XCoreStwsp : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp,
[SDNPHasChain]>;
def XCoreStwsp : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp,
[SDNPHasChain]>;
// These are target-independent nodes, but have target-specific formats.
def SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;

2
lib/VMCore/Verifier.cpp
View File

@ -1395,7 +1395,7 @@ void Verifier::visitIntrinsicFunctionCall(Intrinsic::ID ID, CallInst &CI) {
switch (ID) {
default:
break;
case Intrinsic::dbg_declare: // llvm.dbg.declare
case Intrinsic::dbg_declare: // llvm.dbg.declare
if (Constant *C = dyn_cast<Constant>(CI.getOperand(1)))
Assert1(C && !isa<ConstantPointerNull>(C),
"invalid llvm.dbg.declare intrinsic call", &CI);