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https://github.com/c64scene-ar/llvm-6502.git
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[X86] Convert all the i8imm used by AVX512 and MMX instructions to u8imm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226646 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
951d088ae7
commit
51da87a580
@ -394,7 +394,7 @@ multiclass vinsert_for_size_no_alt<int Opcode,
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SDNodeXForm INSERT_get_vinsert_imm> {
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let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
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def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
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(ins VR512:$src1, From.RC:$src2, i8imm:$src3),
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(ins VR512:$src1, From.RC:$src2, u8imm:$src3),
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"vinsert" # From.EltTypeName # "x" # From.NumElts #
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"\t{$src3, $src2, $src1, $dst|"
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"$dst, $src1, $src2, $src3}",
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@ -405,7 +405,7 @@ multiclass vinsert_for_size_no_alt<int Opcode,
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let mayLoad = 1 in
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def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
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(ins VR512:$src1, From.MemOp:$src2, i8imm:$src3),
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(ins VR512:$src1, From.MemOp:$src2, u8imm:$src3),
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"vinsert" # From.EltTypeName # "x" # From.NumElts #
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"\t{$src3, $src2, $src1, $dst|"
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"$dst, $src1, $src2, $src3}",
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@ -467,12 +467,12 @@ defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
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// vinsertps - insert f32 to XMM
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def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
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(ins VR128X:$src1, VR128X:$src2, i8imm:$src3),
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(ins VR128X:$src1, VR128X:$src2, u8imm:$src3),
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"vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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[(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
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EVEX_4V;
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def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
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(ins VR128X:$src1, f32mem:$src2, i8imm:$src3),
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(ins VR128X:$src1, f32mem:$src2, u8imm:$src3),
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"vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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[(set VR128X:$dst, (X86insertps VR128X:$src1,
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(v4f32 (scalar_to_vector (loadf32 addr:$src2))),
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@ -489,7 +489,7 @@ multiclass vextract_for_size<int Opcode,
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SDNodeXForm EXTRACT_get_vextract_imm> {
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let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
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defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
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(ins VR512:$src1, i8imm:$idx),
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(ins VR512:$src1, u8imm:$idx),
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"vextract" # To.EltTypeName # "x4",
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"$idx, $src1", "$src1, $idx",
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[(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
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@ -497,7 +497,7 @@ multiclass vextract_for_size<int Opcode,
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AVX512AIi8Base, EVEX, EVEX_V512;
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let mayStore = 1 in
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def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
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(ins To.MemOp:$dst, VR512:$src1, i8imm:$src2),
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(ins To.MemOp:$dst, VR512:$src1, u8imm:$src2),
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"vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
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"$dst, $src1, $src2}",
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[]>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
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@ -882,14 +882,14 @@ multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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X86VectorVTInfo _> {
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let ExeDomain = _.ExeDomain in {
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def ri : AVX512AIi8<opc, MRMSrcReg, (outs _.RC:$dst),
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(ins _.RC:$src1, i8imm:$src2),
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(ins _.RC:$src1, u8imm:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set _.RC:$dst,
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(_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>,
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EVEX;
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def mi : AVX512AIi8<opc, MRMSrcMem, (outs _.RC:$dst),
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(ins _.MemOp:$src1, i8imm:$src2),
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(ins _.MemOp:$src1, u8imm:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set _.RC:$dst,
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@ -1403,19 +1403,19 @@ multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
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// Accept explicit immediate argument form instead of comparison code.
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let isAsmParserOnly = 1, hasSideEffects = 0 in {
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def rri_alt : AVX512AIi8<opc, MRMSrcReg,
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(outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, i8imm:$cc),
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(outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
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!strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
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"$dst, $src1, $src2, $cc}"),
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[], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
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let mayLoad = 1 in
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def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
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(outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, i8imm:$cc),
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(outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
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!strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
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"$dst, $src1, $src2, $cc}"),
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[], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
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def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
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(outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
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i8imm:$cc),
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u8imm:$cc),
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!strconcat("vpcmp", Suffix,
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"\t{$cc, $src2, $src1, $dst {${mask}}|",
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"$dst {${mask}}, $src1, $src2, $cc}"),
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@ -1423,7 +1423,7 @@ multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
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let mayLoad = 1 in
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def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
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(outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
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i8imm:$cc),
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u8imm:$cc),
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!strconcat("vpcmp", Suffix,
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"\t{$cc, $src2, $src1, $dst {${mask}}|",
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"$dst {${mask}}, $src1, $src2, $cc}"),
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@ -1460,14 +1460,14 @@ multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
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let isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 1 in {
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def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
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(outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
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i8imm:$cc),
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u8imm:$cc),
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!strconcat("vpcmp", Suffix,
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"\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
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"$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
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[], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
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def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
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(outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
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_.ScalarMemOp:$src2, i8imm:$cc),
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_.ScalarMemOp:$src2, u8imm:$cc),
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!strconcat("vpcmp", Suffix,
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"\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
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"$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
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@ -1959,7 +1959,7 @@ def : Pat<(X86cmp VK1:$src1, (i1 0)),
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multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
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SDNode OpNode> {
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let Predicates = [HasAVX512] in
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def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
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def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, u8imm:$imm),
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!strconcat(OpcodeStr,
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"\t{$imm, $src, $dst|$dst, $src, $imm}"),
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[(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
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@ -3170,14 +3170,14 @@ multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
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SDNode OpNode, PatFrag mem_frag,
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X86MemOperand x86memop, ValueType OpVT> {
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def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, i8imm:$src2),
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(ins RC:$src1, u8imm:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set RC:$dst,
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(OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
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EVEX;
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def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
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(ins x86memop:$src1, i8imm:$src2),
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(ins x86memop:$src1, u8imm:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set RC:$dst,
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@ -3348,12 +3348,12 @@ def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
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multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
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string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
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defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
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(ins _.RC:$src1, i8imm:$src2), OpcodeStr,
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(ins _.RC:$src1, u8imm:$src2), OpcodeStr,
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"$src2, $src1", "$src1, $src2",
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(_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
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" ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIi8Base, EVEX_4V;
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defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
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(ins _.MemOp:$src1, i8imm:$src2), OpcodeStr,
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(ins _.MemOp:$src1, u8imm:$src2), OpcodeStr,
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"$src2, $src1", "$src1, $src2",
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(_.VT (OpNode (_.MemOpFrag addr:$src1), (i8 imm:$src2))),
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" ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIi8Base, EVEX_4V;
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@ -5049,14 +5049,14 @@ multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
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ValueType vt, string OpcodeStr, PatFrag mem_frag,
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Domain d> {
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def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, x86memop:$src2, i8imm:$src3),
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(ins RC:$src1, x86memop:$src2, u8imm:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
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(i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
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EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
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def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, i8imm:$src3),
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(ins RC:$src1, RC:$src2, u8imm:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
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@ -5083,7 +5083,7 @@ def : Pat<(v8i64 (X86Shufp VR512:$src1,
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multiclass avx512_valign<X86VectorVTInfo _> {
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defm rri : AVX512_maskable<0x03, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.RC:$src2, i8imm:$src3),
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(ins _.RC:$src1, _.RC:$src2, u8imm:$src3),
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"valign"##_.Suffix,
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"$src3, $src2, $src1", "$src1, $src2, $src3",
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(_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
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@ -5096,7 +5096,7 @@ multiclass avx512_valign<X86VectorVTInfo _> {
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let mayLoad = 1 in
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def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst),
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(ins _.RC:$src1, _.MemOp:$src2, i8imm:$src3),
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(ins _.RC:$src1, _.MemOp:$src2, u8imm:$src3),
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!strconcat("valign"##_.Suffix,
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"\t{$src3, $src2, $src1, $dst|"
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"$dst, $src1, $src2, $src3}"),
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@ -170,12 +170,12 @@ multiclass SS3I_binop_rm_int_mm<bits<8> opc, string OpcodeStr,
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/// PALIGN MMX instructions (require SSSE3).
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multiclass ssse3_palign_mm<string asm, Intrinsic IntId> {
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def R64irr : MMXSS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
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(ins VR64:$src1, VR64:$src2, i8imm:$src3),
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(ins VR64:$src1, VR64:$src2, u8imm:$src3),
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!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR64:$dst, (IntId VR64:$src1, VR64:$src2, (i8 imm:$src3)))]>,
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Sched<[WriteShuffle]>;
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def R64irm : MMXSS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
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(ins VR64:$src1, i64mem:$src2, i8imm:$src3),
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(ins VR64:$src1, i64mem:$src2, u8imm:$src3),
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!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR64:$dst, (IntId VR64:$src1,
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(bitconvert (load_mmx addr:$src2)), (i8 imm:$src3)))]>,
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@ -518,13 +518,13 @@ defm MMX_PSHUFB : SS3I_binop_rm_int_mm<0x00, "pshufb", int_x86_ssse3_pshuf_b,
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MMX_PSHUF_ITINS>;
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def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg,
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(outs VR64:$dst), (ins VR64:$src1, i8imm:$src2),
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(outs VR64:$dst), (ins VR64:$src1, u8imm:$src2),
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"pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set VR64:$dst,
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(int_x86_sse_pshuf_w VR64:$src1, imm:$src2))],
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IIC_MMX_PSHUF>, Sched<[WriteShuffle]>;
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def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
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(outs VR64:$dst), (ins i64mem:$src1, i8imm:$src2),
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(outs VR64:$dst), (ins i64mem:$src1, u8imm:$src2),
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"pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set VR64:$dst,
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(int_x86_sse_pshuf_w (load_mmx addr:$src1),
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