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Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139415 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
2011-09-09 21:48:23 +00:00
parent 13d8baa3fc
commit 51f6a7abf2
10 changed files with 71 additions and 24 deletions
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18
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@ -426,6 +426,8 @@ static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
// post-pass.
MCDisassembler::DecodeStatus
ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
MCDisassembler::DecodeStatus S = Success;
// A few instructions actually have predicates encoded in them. Don't
// try to overwrite it if we're seeing one of those.
switch (MI.getOpcode()) {
@ -436,8 +438,16 @@ ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
// Some instructions (mostly conditional branches) are not
// allowed in IT blocks.
if (!ITBlock.empty())
return SoftFail;
return Success;
S = SoftFail;
else
return Success;
break;
case ARM::tB:
case ARM::t2B:
// Some instructions (mostly unconditional branches) can
// only appears at the end of, or outside of, an IT.
if (ITBlock.size() > 1)
S = SoftFail;
break;
default:
break;
@ -466,7 +476,7 @@ ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
MI.insert(I, MCOperand::CreateReg(0));
else
MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
return Success;
return S;
}
}
@ -477,7 +487,7 @@ ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
else
MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
return Success;
return S;
}
// Thumb VFP instructions are a special case. Because we share their