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Add some options to disable various code gen optimizations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86044 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -31,6 +31,22 @@ namespace llvm {
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bool EnableFastISel;
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}
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static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
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cl::desc("Disable Post Regalloc"));
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static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
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cl::desc("Disable branch folding"));
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static cl::opt<bool> DisableCodePlace("disable-code-place", cl::Hidden,
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cl::desc("Disable code placement"));
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static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
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cl::desc("Disable Stack Slot Coloring"));
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static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
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cl::desc("Disable Machine LICM"));
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static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
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cl::desc("Disable Machine Sinking"));
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static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
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cl::desc("Disable Loop Strength Reduction Pass"));
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static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
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cl::desc("Disable Codegen Prepare"));
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static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
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cl::desc("Print LLVM IR produced by the loop-reduce pass"));
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static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
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@ -208,7 +224,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
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// Standard LLVM-Level Passes.
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// Run loop strength reduction before anything else.
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if (OptLevel != CodeGenOpt::None) {
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if (OptLevel != CodeGenOpt::None && !DisableLSR) {
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PM.add(createLoopStrengthReducePass(getTargetLowering()));
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if (PrintLSR)
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PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &errs()));
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@ -236,7 +252,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
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// Make sure that no unreachable blocks are instruction selected.
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PM.add(createUnreachableBlockEliminationPass());
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if (OptLevel != CodeGenOpt::None)
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if (OptLevel != CodeGenOpt::None && !DisableCGP)
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PM.add(createCodeGenPreparePass(getTargetLowering()));
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PM.add(createStackProtectorPass(getTargetLowering()));
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@ -265,8 +281,10 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
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/* allowDoubleDefs= */ true);
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if (OptLevel != CodeGenOpt::None) {
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PM.add(createMachineLICMPass());
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PM.add(createMachineSinkingPass());
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if (!DisableMachineLICM)
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PM.add(createMachineLICMPass());
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if (!DisableMachineSink)
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PM.add(createMachineSinkingPass());
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printAndVerify(PM, "After MachineLICM and MachineSinking",
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/* allowDoubleDefs= */ true);
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}
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@ -281,7 +299,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
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printAndVerify(PM, "After Register Allocation");
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// Perform stack slot coloring.
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if (OptLevel != CodeGenOpt::None) {
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if (OptLevel != CodeGenOpt::None && !DisableSSC) {
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// FIXME: Re-enable coloring with register when it's capable of adding
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// kill markers.
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PM.add(createStackSlotColoringPass(false));
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@ -304,13 +322,13 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
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printAndVerify(PM, "After PreSched2 passes");
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// Second pass scheduler.
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if (OptLevel != CodeGenOpt::None) {
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if (OptLevel != CodeGenOpt::None && !DisablePostRA) {
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PM.add(createPostRAScheduler(OptLevel));
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printAndVerify(PM, "After PostRAScheduler");
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}
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// Branch folding must be run after regalloc and prolog/epilog insertion.
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if (OptLevel != CodeGenOpt::None) {
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if (OptLevel != CodeGenOpt::None && !DisableBranchFold) {
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PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
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printAndVerify(PM, "After BranchFolding");
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}
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@ -327,7 +345,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
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if (addPreEmitPass(PM, OptLevel))
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printAndVerify(PM, "After PreEmit passes");
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if (OptLevel != CodeGenOpt::None) {
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if (OptLevel != CodeGenOpt::None && !DisableCodePlace) {
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PM.add(createCodePlacementOptPass());
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printAndVerify(PM, "After CodePlacementOpt");
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}
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