From 522ce975327e1aeba8317b233cdb54366e2645b5 Mon Sep 17 00:00:00 2001 From: Bob Wilson Date: Mon, 28 Sep 2009 14:30:20 +0000 Subject: [PATCH] Pass the optimization level when constructing the ARM instruction selector. Otherwise, it is always set to "default", which prevents debug info from even being generated during isel. Radar 7250345. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82988 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARM.h | 3 ++- lib/Target/ARM/ARMISelDAGToDAG.cpp | 10 ++++++---- lib/Target/ARM/ARMTargetMachine.cpp | 2 +- 3 files changed, 9 insertions(+), 6 deletions(-) diff --git a/lib/Target/ARM/ARM.h b/lib/Target/ARM/ARM.h index e95dfc02b60..487ce1dd434 100644 --- a/lib/Target/ARM/ARM.h +++ b/lib/Target/ARM/ARM.h @@ -92,7 +92,8 @@ inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) { } } -FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM); +FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM, + CodeGenOpt::Level OptLevel); FunctionPass *createARMCodeEmitterPass(ARMBaseTargetMachine &TM, MachineCodeEmitter &MCE); diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index d165a09997e..53f2282c4f0 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -49,8 +49,9 @@ class ARMDAGToDAGISel : public SelectionDAGISel { const ARMSubtarget *Subtarget; public: - explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm) - : SelectionDAGISel(tm), TM(tm), + explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm, + CodeGenOpt::Level OptLevel) + : SelectionDAGISel(tm, OptLevel), TM(tm), Subtarget(&TM.getSubtarget()) { } @@ -1566,6 +1567,7 @@ SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, /// createARMISelDag - This pass converts a legalized DAG into a /// ARM-specific DAG, ready for instruction scheduling. /// -FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM) { - return new ARMDAGToDAGISel(TM); +FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM, + CodeGenOpt::Level OptLevel) { + return new ARMDAGToDAGISel(TM, OptLevel); } diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp index 045df1542f8..dcb64c5131c 100644 --- a/lib/Target/ARM/ARMTargetMachine.cpp +++ b/lib/Target/ARM/ARMTargetMachine.cpp @@ -86,7 +86,7 @@ ThumbTargetMachine::ThumbTargetMachine(const Target &T, const std::string &TT, // Pass Pipeline Configuration bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel) { - PM.add(createARMISelDag(*this)); + PM.add(createARMISelDag(*this, OptLevel)); return false; }