mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-17 03:30:28 +00:00
integrate the 64-bit shifts into X86InstrShiftRotate.td. Enough for tonight.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115608 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
5f58e84af8
commit
5249ff34fb
@ -444,227 +444,6 @@ def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
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} // Defs = [EFLAGS], CodeSize
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} // Defs = [EFLAGS], CodeSize
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let Defs = [EFLAGS] in {
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// Shift instructions
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let Constraints = "$src1 = $dst" in {
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let Uses = [CL] in
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def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
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"shl{q}\t{%cl, $dst|$dst, %CL}",
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[(set GR64:$dst, (shl GR64:$src1, CL))]>;
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let isConvertibleToThreeAddress = 1 in // Can transform into LEA.
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def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),
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(ins GR64:$src1, i8imm:$src2),
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"shl{q}\t{$src2, $dst|$dst, $src2}",
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[(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
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// NOTE: We don't include patterns for shifts of a register by one, because
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// 'add reg,reg' is cheaper.
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def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
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"shl{q}\t$dst", []>;
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} // Constraints = "$src1 = $dst"
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let Uses = [CL] in
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def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
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"shl{q}\t{%cl, $dst|$dst, %CL}",
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[(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>;
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def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
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"shl{q}\t{$src, $dst|$dst, $src}",
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[(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
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def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
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"shl{q}\t$dst",
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[(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
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let Constraints = "$src1 = $dst" in {
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let Uses = [CL] in
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def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
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"shr{q}\t{%cl, $dst|$dst, %CL}",
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[(set GR64:$dst, (srl GR64:$src1, CL))]>;
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def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
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"shr{q}\t{$src2, $dst|$dst, $src2}",
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[(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>;
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def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
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"shr{q}\t$dst",
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[(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>;
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} // Constraints = "$src1 = $dst"
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let Uses = [CL] in
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def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
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"shr{q}\t{%cl, $dst|$dst, %CL}",
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[(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>;
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def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
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"shr{q}\t{$src, $dst|$dst, $src}",
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[(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
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def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
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"shr{q}\t$dst",
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[(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
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let Constraints = "$src1 = $dst" in {
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let Uses = [CL] in
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def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
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"sar{q}\t{%cl, $dst|$dst, %CL}",
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[(set GR64:$dst, (sra GR64:$src1, CL))]>;
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def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst),
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(ins GR64:$src1, i8imm:$src2),
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"sar{q}\t{$src2, $dst|$dst, $src2}",
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[(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>;
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def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
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"sar{q}\t$dst",
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[(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>;
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} // Constraints = "$src = $dst"
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let Uses = [CL] in
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def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
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"sar{q}\t{%cl, $dst|$dst, %CL}",
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[(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>;
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def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
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"sar{q}\t{$src, $dst|$dst, $src}",
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[(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
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def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
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"sar{q}\t$dst",
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[(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
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// Rotate instructions
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let Constraints = "$src = $dst" in {
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def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src),
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"rcl{q}\t{1, $dst|$dst, 1}", []>;
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def RCL64ri : RIi8<0xC1, MRM2r, (outs GR64:$dst), (ins GR64:$src, i8imm:$cnt),
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"rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>;
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def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src),
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"rcr{q}\t{1, $dst|$dst, 1}", []>;
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def RCR64ri : RIi8<0xC1, MRM3r, (outs GR64:$dst), (ins GR64:$src, i8imm:$cnt),
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"rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>;
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let Uses = [CL] in {
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def RCL64rCL : RI<0xD3, MRM2r, (outs GR64:$dst), (ins GR64:$src),
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"rcl{q}\t{%cl, $dst|$dst, CL}", []>;
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def RCR64rCL : RI<0xD3, MRM3r, (outs GR64:$dst), (ins GR64:$src),
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"rcr{q}\t{%cl, $dst|$dst, CL}", []>;
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}
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} // Constraints = "$src = $dst"
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def RCL64m1 : RI<0xD1, MRM2m, (outs), (ins i64mem:$dst),
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"rcl{q}\t{1, $dst|$dst, 1}", []>;
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def RCL64mi : RIi8<0xC1, MRM2m, (outs), (ins i64mem:$dst, i8imm:$cnt),
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"rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>;
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def RCR64m1 : RI<0xD1, MRM3m, (outs), (ins i64mem:$dst),
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"rcr{q}\t{1, $dst|$dst, 1}", []>;
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def RCR64mi : RIi8<0xC1, MRM3m, (outs), (ins i64mem:$dst, i8imm:$cnt),
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"rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>;
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let Uses = [CL] in {
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def RCL64mCL : RI<0xD3, MRM2m, (outs), (ins i64mem:$dst),
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"rcl{q}\t{%cl, $dst|$dst, CL}", []>;
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def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst),
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"rcr{q}\t{%cl, $dst|$dst, CL}", []>;
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}
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let Constraints = "$src1 = $dst" in {
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let Uses = [CL] in
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def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
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"rol{q}\t{%cl, $dst|$dst, %CL}",
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[(set GR64:$dst, (rotl GR64:$src1, CL))]>;
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def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst),
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(ins GR64:$src1, i8imm:$src2),
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"rol{q}\t{$src2, $dst|$dst, $src2}",
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[(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>;
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def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
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"rol{q}\t$dst",
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[(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>;
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} // Constraints = "$src1 = $dst"
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let Uses = [CL] in
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def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst),
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"rol{q}\t{%cl, $dst|$dst, %CL}",
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[(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>;
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def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src),
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"rol{q}\t{$src, $dst|$dst, $src}",
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[(store (rotl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
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def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
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"rol{q}\t$dst",
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[(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
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let Constraints = "$src1 = $dst" in {
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let Uses = [CL] in
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def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
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"ror{q}\t{%cl, $dst|$dst, %CL}",
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[(set GR64:$dst, (rotr GR64:$src1, CL))]>;
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def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst),
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(ins GR64:$src1, i8imm:$src2),
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"ror{q}\t{$src2, $dst|$dst, $src2}",
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[(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>;
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def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
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"ror{q}\t$dst",
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[(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>;
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} // Constraints = "$src1 = $dst"
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let Uses = [CL] in
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def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
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"ror{q}\t{%cl, $dst|$dst, %CL}",
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[(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>;
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def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
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"ror{q}\t{$src, $dst|$dst, $src}",
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[(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
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def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
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"ror{q}\t$dst",
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[(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
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// Double shift instructions (generalizations of rotate)
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let Constraints = "$src1 = $dst" in {
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let Uses = [CL] in {
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def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst),
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(ins GR64:$src1, GR64:$src2),
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"shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
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[(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))]>,
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TB;
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def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst),
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(ins GR64:$src1, GR64:$src2),
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"shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
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[(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))]>,
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TB;
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}
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let isCommutable = 1 in { // FIXME: Update X86InstrInfo::commuteInstruction
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def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
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(outs GR64:$dst),
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(ins GR64:$src1, GR64:$src2, i8imm:$src3),
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"shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
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[(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
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(i8 imm:$src3)))]>,
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TB;
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def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
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(outs GR64:$dst),
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(ins GR64:$src1, GR64:$src2, i8imm:$src3),
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"shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
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[(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
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(i8 imm:$src3)))]>,
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TB;
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} // isCommutable
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} // Constraints = "$src1 = $dst"
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let Uses = [CL] in {
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def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
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"shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
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[(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
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addr:$dst)]>, TB;
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def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
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"shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
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[(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
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addr:$dst)]>, TB;
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}
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def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
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(outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
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"shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
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[(store (X86shld (loadi64 addr:$dst), GR64:$src2,
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(i8 imm:$src3)), addr:$dst)]>,
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TB;
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def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
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(outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
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"shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
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[(store (X86shrd (loadi64 addr:$dst), GR64:$src2,
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(i8 imm:$src3)), addr:$dst)]>,
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TB;
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} // Defs = [EFLAGS]
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Logical Instructions...
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// Logical Instructions...
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@ -26,6 +26,9 @@ def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
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def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
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def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
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"shl{l}\t{%cl, $dst|$dst, CL}",
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"shl{l}\t{%cl, $dst|$dst, CL}",
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[(set GR32:$dst, (shl GR32:$src1, CL))]>;
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[(set GR32:$dst, (shl GR32:$src1, CL))]>;
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def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
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"shl{q}\t{%cl, $dst|$dst, %CL}",
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[(set GR64:$dst, (shl GR64:$src1, CL))]>;
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} // Uses = [CL]
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} // Uses = [CL]
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def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
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def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
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@ -39,20 +42,27 @@ def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
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def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
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def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
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"shl{l}\t{$src2, $dst|$dst, $src2}",
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"shl{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
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[(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
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def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),
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(ins GR64:$src1, i8imm:$src2),
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"shl{q}\t{$src2, $dst|$dst, $src2}",
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[(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
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// NOTE: We don't include patterns for shifts of a register by one, because
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// NOTE: We don't include patterns for shifts of a register by one, because
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// 'add reg,reg' is cheaper.
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// 'add reg,reg' is cheaper (and we have a Pat pattern for shift-by-one).
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|
||||||
def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
|
def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
|
||||||
"shl{b}\t$dst", []>;
|
"shl{b}\t$dst", []>;
|
||||||
def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
|
def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
|
||||||
"shl{w}\t$dst", []>, OpSize;
|
"shl{w}\t$dst", []>, OpSize;
|
||||||
def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
|
def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
|
||||||
"shl{l}\t$dst", []>;
|
"shl{l}\t$dst", []>;
|
||||||
|
def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
|
||||||
|
"shl{q}\t$dst", []>;
|
||||||
} // isConvertibleToThreeAddress = 1
|
} // isConvertibleToThreeAddress = 1
|
||||||
} // Constraints = "$src = $dst"
|
} // Constraints = "$src = $dst"
|
||||||
|
|
||||||
|
|
||||||
|
// FIXME: Why do we need an explicit "Uses = [CL]" when the instr has a pattern
|
||||||
|
// using CL?
|
||||||
let Uses = [CL] in {
|
let Uses = [CL] in {
|
||||||
def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
|
def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
|
||||||
"shl{b}\t{%cl, $dst|$dst, CL}",
|
"shl{b}\t{%cl, $dst|$dst, CL}",
|
||||||
@ -63,6 +73,9 @@ def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
|
|||||||
def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
|
def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
|
||||||
"shl{l}\t{%cl, $dst|$dst, CL}",
|
"shl{l}\t{%cl, $dst|$dst, CL}",
|
||||||
[(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
|
[(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
|
||||||
|
def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
|
||||||
|
"shl{q}\t{%cl, $dst|$dst, %CL}",
|
||||||
|
[(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>;
|
||||||
}
|
}
|
||||||
def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
|
def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
|
||||||
"shl{b}\t{$src, $dst|$dst, $src}",
|
"shl{b}\t{$src, $dst|$dst, $src}",
|
||||||
@ -74,6 +87,9 @@ def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
|
|||||||
def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
|
def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
|
||||||
"shl{l}\t{$src, $dst|$dst, $src}",
|
"shl{l}\t{$src, $dst|$dst, $src}",
|
||||||
[(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
|
[(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
|
||||||
|
def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
|
||||||
|
"shl{q}\t{$src, $dst|$dst, $src}",
|
||||||
|
[(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
|
||||||
|
|
||||||
// Shift by 1
|
// Shift by 1
|
||||||
def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
|
def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
|
||||||
@ -86,6 +102,9 @@ def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
|
|||||||
def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
|
def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
|
||||||
"shl{l}\t$dst",
|
"shl{l}\t$dst",
|
||||||
[(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
|
[(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
|
||||||
|
def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
|
||||||
|
"shl{q}\t$dst",
|
||||||
|
[(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
|
||||||
|
|
||||||
let Constraints = "$src1 = $dst" in {
|
let Constraints = "$src1 = $dst" in {
|
||||||
let Uses = [CL] in {
|
let Uses = [CL] in {
|
||||||
@ -98,6 +117,9 @@ def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
|
|||||||
def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
|
def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
|
||||||
"shr{l}\t{%cl, $dst|$dst, CL}",
|
"shr{l}\t{%cl, $dst|$dst, CL}",
|
||||||
[(set GR32:$dst, (srl GR32:$src1, CL))]>;
|
[(set GR32:$dst, (srl GR32:$src1, CL))]>;
|
||||||
|
def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
|
||||||
|
"shr{q}\t{%cl, $dst|$dst, %CL}",
|
||||||
|
[(set GR64:$dst, (srl GR64:$src1, CL))]>;
|
||||||
}
|
}
|
||||||
|
|
||||||
def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
|
def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
|
||||||
@ -109,8 +131,11 @@ def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
|
|||||||
def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
|
def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
|
||||||
"shr{l}\t{$src2, $dst|$dst, $src2}",
|
"shr{l}\t{$src2, $dst|$dst, $src2}",
|
||||||
[(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
|
[(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
|
||||||
|
def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
|
||||||
|
"shr{q}\t{$src2, $dst|$dst, $src2}",
|
||||||
|
[(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>;
|
||||||
|
|
||||||
// Shift by 1
|
// Shift right by 1
|
||||||
def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
|
def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
|
||||||
"shr{b}\t$dst",
|
"shr{b}\t$dst",
|
||||||
[(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
|
[(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
|
||||||
@ -120,6 +145,9 @@ def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
|
|||||||
def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
|
def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
|
||||||
"shr{l}\t$dst",
|
"shr{l}\t$dst",
|
||||||
[(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
|
[(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
|
||||||
|
def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
|
||||||
|
"shr{q}\t$dst",
|
||||||
|
[(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>;
|
||||||
} // Constraints = "$src = $dst"
|
} // Constraints = "$src = $dst"
|
||||||
|
|
||||||
|
|
||||||
@ -134,6 +162,9 @@ def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
|
|||||||
def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
|
def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
|
||||||
"shr{l}\t{%cl, $dst|$dst, CL}",
|
"shr{l}\t{%cl, $dst|$dst, CL}",
|
||||||
[(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
|
[(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
|
||||||
|
def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
|
||||||
|
"shr{q}\t{%cl, $dst|$dst, %CL}",
|
||||||
|
[(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>;
|
||||||
}
|
}
|
||||||
def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
|
def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
|
||||||
"shr{b}\t{$src, $dst|$dst, $src}",
|
"shr{b}\t{$src, $dst|$dst, $src}",
|
||||||
@ -145,6 +176,9 @@ def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
|
|||||||
def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
|
def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
|
||||||
"shr{l}\t{$src, $dst|$dst, $src}",
|
"shr{l}\t{$src, $dst|$dst, $src}",
|
||||||
[(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
|
[(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
|
||||||
|
def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
|
||||||
|
"shr{q}\t{$src, $dst|$dst, $src}",
|
||||||
|
[(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
|
||||||
|
|
||||||
// Shift by 1
|
// Shift by 1
|
||||||
def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
|
def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
|
||||||
@ -156,6 +190,9 @@ def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
|
|||||||
def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
|
def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
|
||||||
"shr{l}\t$dst",
|
"shr{l}\t$dst",
|
||||||
[(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
|
[(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
|
||||||
|
def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
|
||||||
|
"shr{q}\t$dst",
|
||||||
|
[(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
|
||||||
|
|
||||||
let Constraints = "$src1 = $dst" in {
|
let Constraints = "$src1 = $dst" in {
|
||||||
let Uses = [CL] in {
|
let Uses = [CL] in {
|
||||||
@ -168,6 +205,9 @@ def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
|
|||||||
def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
|
def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
|
||||||
"sar{l}\t{%cl, $dst|$dst, CL}",
|
"sar{l}\t{%cl, $dst|$dst, CL}",
|
||||||
[(set GR32:$dst, (sra GR32:$src1, CL))]>;
|
[(set GR32:$dst, (sra GR32:$src1, CL))]>;
|
||||||
|
def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
|
||||||
|
"sar{q}\t{%cl, $dst|$dst, %CL}",
|
||||||
|
[(set GR64:$dst, (sra GR64:$src1, CL))]>;
|
||||||
}
|
}
|
||||||
|
|
||||||
def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
|
def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
|
||||||
@ -180,6 +220,10 @@ def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
|
|||||||
def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
|
def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
|
||||||
"sar{l}\t{$src2, $dst|$dst, $src2}",
|
"sar{l}\t{$src2, $dst|$dst, $src2}",
|
||||||
[(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
|
[(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
|
||||||
|
def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst),
|
||||||
|
(ins GR64:$src1, i8imm:$src2),
|
||||||
|
"sar{q}\t{$src2, $dst|$dst, $src2}",
|
||||||
|
[(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>;
|
||||||
|
|
||||||
// Shift by 1
|
// Shift by 1
|
||||||
def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
|
def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
|
||||||
@ -191,6 +235,9 @@ def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
|
|||||||
def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
|
def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
|
||||||
"sar{l}\t$dst",
|
"sar{l}\t$dst",
|
||||||
[(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
|
[(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
|
||||||
|
def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
|
||||||
|
"sar{q}\t$dst",
|
||||||
|
[(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>;
|
||||||
} // Constraints = "$src = $dst"
|
} // Constraints = "$src = $dst"
|
||||||
|
|
||||||
|
|
||||||
@ -204,6 +251,9 @@ def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
|
|||||||
def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
|
def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
|
||||||
"sar{l}\t{%cl, $dst|$dst, CL}",
|
"sar{l}\t{%cl, $dst|$dst, CL}",
|
||||||
[(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
|
[(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
|
||||||
|
def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
|
||||||
|
"sar{q}\t{%cl, $dst|$dst, %CL}",
|
||||||
|
[(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>;
|
||||||
}
|
}
|
||||||
def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
|
def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
|
||||||
"sar{b}\t{$src, $dst|$dst, $src}",
|
"sar{b}\t{$src, $dst|$dst, $src}",
|
||||||
@ -215,6 +265,9 @@ def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
|
|||||||
def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
|
def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
|
||||||
"sar{l}\t{$src, $dst|$dst, $src}",
|
"sar{l}\t{$src, $dst|$dst, $src}",
|
||||||
[(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
|
[(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
|
||||||
|
def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
|
||||||
|
"sar{q}\t{$src, $dst|$dst, $src}",
|
||||||
|
[(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
|
||||||
|
|
||||||
// Shift by 1
|
// Shift by 1
|
||||||
def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
|
def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
|
||||||
@ -227,6 +280,9 @@ def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
|
|||||||
def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
|
def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
|
||||||
"sar{l}\t$dst",
|
"sar{l}\t$dst",
|
||||||
[(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
|
[(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
|
||||||
|
def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
|
||||||
|
"sar{q}\t$dst",
|
||||||
|
[(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
|
||||||
|
|
||||||
//===----------------------------------------------------------------------===//
|
//===----------------------------------------------------------------------===//
|
||||||
// Rotate instructions
|
// Rotate instructions
|
||||||
@ -235,57 +291,70 @@ def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
|
|||||||
let Constraints = "$src1 = $dst" in {
|
let Constraints = "$src1 = $dst" in {
|
||||||
def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
|
def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
|
||||||
"rcl{b}\t{1, $dst|$dst, 1}", []>;
|
"rcl{b}\t{1, $dst|$dst, 1}", []>;
|
||||||
let Uses = [CL] in {
|
|
||||||
def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
|
|
||||||
"rcl{b}\t{%cl, $dst|$dst, CL}", []>;
|
|
||||||
}
|
|
||||||
def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
|
def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
|
||||||
"rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
|
"rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
|
||||||
|
let Uses = [CL] in
|
||||||
|
def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
|
||||||
|
"rcl{b}\t{%cl, $dst|$dst, CL}", []>;
|
||||||
|
|
||||||
def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
|
def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
|
||||||
"rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
|
"rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
|
||||||
let Uses = [CL] in {
|
|
||||||
def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
|
|
||||||
"rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
|
|
||||||
}
|
|
||||||
def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
|
def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
|
||||||
"rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
|
"rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
|
||||||
|
let Uses = [CL] in
|
||||||
|
def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
|
||||||
|
"rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
|
||||||
|
|
||||||
def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
|
def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
|
||||||
"rcl{l}\t{1, $dst|$dst, 1}", []>;
|
"rcl{l}\t{1, $dst|$dst, 1}", []>;
|
||||||
let Uses = [CL] in {
|
|
||||||
def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
|
|
||||||
"rcl{l}\t{%cl, $dst|$dst, CL}", []>;
|
|
||||||
}
|
|
||||||
def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
|
def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
|
||||||
"rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
|
"rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
|
||||||
|
let Uses = [CL] in
|
||||||
|
def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
|
||||||
|
"rcl{l}\t{%cl, $dst|$dst, CL}", []>;
|
||||||
|
|
||||||
|
|
||||||
|
def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src1),
|
||||||
|
"rcl{q}\t{1, $dst|$dst, 1}", []>;
|
||||||
|
def RCL64ri : RIi8<0xC1, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$cnt),
|
||||||
|
"rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>;
|
||||||
|
let Uses = [CL] in
|
||||||
|
def RCL64rCL : RI<0xD3, MRM2r, (outs GR64:$dst), (ins GR64:$src1),
|
||||||
|
"rcl{q}\t{%cl, $dst|$dst, CL}", []>;
|
||||||
|
|
||||||
|
|
||||||
def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
|
def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
|
||||||
"rcr{b}\t{1, $dst|$dst, 1}", []>;
|
"rcr{b}\t{1, $dst|$dst, 1}", []>;
|
||||||
let Uses = [CL] in {
|
|
||||||
def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
|
|
||||||
"rcr{b}\t{%cl, $dst|$dst, CL}", []>;
|
|
||||||
}
|
|
||||||
def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
|
def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
|
||||||
"rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
|
"rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
|
||||||
|
let Uses = [CL] in
|
||||||
|
def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
|
||||||
|
"rcr{b}\t{%cl, $dst|$dst, CL}", []>;
|
||||||
|
|
||||||
def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
|
def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
|
||||||
"rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
|
"rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
|
||||||
let Uses = [CL] in {
|
|
||||||
def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
|
|
||||||
"rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
|
|
||||||
}
|
|
||||||
def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
|
def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
|
||||||
"rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
|
"rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
|
||||||
|
let Uses = [CL] in
|
||||||
|
def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
|
||||||
|
"rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
|
||||||
|
|
||||||
def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
|
def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
|
||||||
"rcr{l}\t{1, $dst|$dst, 1}", []>;
|
"rcr{l}\t{1, $dst|$dst, 1}", []>;
|
||||||
let Uses = [CL] in {
|
|
||||||
def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
|
|
||||||
"rcr{l}\t{%cl, $dst|$dst, CL}", []>;
|
|
||||||
}
|
|
||||||
def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
|
def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
|
||||||
"rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
|
"rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
|
||||||
|
let Uses = [CL] in
|
||||||
|
def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
|
||||||
|
"rcr{l}\t{%cl, $dst|$dst, CL}", []>;
|
||||||
|
|
||||||
|
def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
|
||||||
|
"rcr{q}\t{1, $dst|$dst, 1}", []>;
|
||||||
|
def RCR64ri : RIi8<0xC1, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$cnt),
|
||||||
|
"rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>;
|
||||||
|
let Uses = [CL] in
|
||||||
|
def RCR64rCL : RI<0xD3, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
|
||||||
|
"rcr{q}\t{%cl, $dst|$dst, CL}", []>;
|
||||||
|
|
||||||
} // Constraints = "$src = $dst"
|
} // Constraints = "$src = $dst"
|
||||||
|
|
||||||
def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst),
|
def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst),
|
||||||
@ -300,6 +369,11 @@ def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst),
|
|||||||
"rcl{l}\t{1, $dst|$dst, 1}", []>;
|
"rcl{l}\t{1, $dst|$dst, 1}", []>;
|
||||||
def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, i8imm:$cnt),
|
def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, i8imm:$cnt),
|
||||||
"rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
|
"rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
|
||||||
|
def RCL64m1 : RI<0xD1, MRM2m, (outs), (ins i64mem:$dst),
|
||||||
|
"rcl{q}\t{1, $dst|$dst, 1}", []>;
|
||||||
|
def RCL64mi : RIi8<0xC1, MRM2m, (outs), (ins i64mem:$dst, i8imm:$cnt),
|
||||||
|
"rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>;
|
||||||
|
|
||||||
def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst),
|
def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst),
|
||||||
"rcr{b}\t{1, $dst|$dst, 1}", []>;
|
"rcr{b}\t{1, $dst|$dst, 1}", []>;
|
||||||
def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, i8imm:$cnt),
|
def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, i8imm:$cnt),
|
||||||
@ -312,6 +386,10 @@ def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst),
|
|||||||
"rcr{l}\t{1, $dst|$dst, 1}", []>;
|
"rcr{l}\t{1, $dst|$dst, 1}", []>;
|
||||||
def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, i8imm:$cnt),
|
def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, i8imm:$cnt),
|
||||||
"rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
|
"rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
|
||||||
|
def RCR64m1 : RI<0xD1, MRM3m, (outs), (ins i64mem:$dst),
|
||||||
|
"rcr{q}\t{1, $dst|$dst, 1}", []>;
|
||||||
|
def RCR64mi : RIi8<0xC1, MRM3m, (outs), (ins i64mem:$dst, i8imm:$cnt),
|
||||||
|
"rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>;
|
||||||
|
|
||||||
let Uses = [CL] in {
|
let Uses = [CL] in {
|
||||||
def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst),
|
def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst),
|
||||||
@ -320,12 +398,17 @@ def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst),
|
|||||||
"rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
|
"rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
|
||||||
def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),
|
def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),
|
||||||
"rcl{l}\t{%cl, $dst|$dst, CL}", []>;
|
"rcl{l}\t{%cl, $dst|$dst, CL}", []>;
|
||||||
|
def RCL64mCL : RI<0xD3, MRM2m, (outs), (ins i64mem:$dst),
|
||||||
|
"rcl{q}\t{%cl, $dst|$dst, CL}", []>;
|
||||||
|
|
||||||
def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst),
|
def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst),
|
||||||
"rcr{b}\t{%cl, $dst|$dst, CL}", []>;
|
"rcr{b}\t{%cl, $dst|$dst, CL}", []>;
|
||||||
def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),
|
def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),
|
||||||
"rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
|
"rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
|
||||||
def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
|
def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
|
||||||
"rcr{l}\t{%cl, $dst|$dst, CL}", []>;
|
"rcr{l}\t{%cl, $dst|$dst, CL}", []>;
|
||||||
|
def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst),
|
||||||
|
"rcr{q}\t{%cl, $dst|$dst, CL}", []>;
|
||||||
}
|
}
|
||||||
|
|
||||||
let Constraints = "$src1 = $dst" in {
|
let Constraints = "$src1 = $dst" in {
|
||||||
@ -340,6 +423,9 @@ def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
|
|||||||
def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
|
def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
|
||||||
"rol{l}\t{%cl, $dst|$dst, CL}",
|
"rol{l}\t{%cl, $dst|$dst, CL}",
|
||||||
[(set GR32:$dst, (rotl GR32:$src1, CL))]>;
|
[(set GR32:$dst, (rotl GR32:$src1, CL))]>;
|
||||||
|
def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
|
||||||
|
"rol{q}\t{%cl, $dst|$dst, %CL}",
|
||||||
|
[(set GR64:$dst, (rotl GR64:$src1, CL))]>;
|
||||||
}
|
}
|
||||||
|
|
||||||
def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
|
def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
|
||||||
@ -352,6 +438,10 @@ def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
|
|||||||
def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
|
def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
|
||||||
"rol{l}\t{$src2, $dst|$dst, $src2}",
|
"rol{l}\t{$src2, $dst|$dst, $src2}",
|
||||||
[(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
|
[(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
|
||||||
|
def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst),
|
||||||
|
(ins GR64:$src1, i8imm:$src2),
|
||||||
|
"rol{q}\t{$src2, $dst|$dst, $src2}",
|
||||||
|
[(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>;
|
||||||
|
|
||||||
// Rotate by 1
|
// Rotate by 1
|
||||||
def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
|
def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
|
||||||
@ -363,6 +453,9 @@ def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
|
|||||||
def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
|
def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
|
||||||
"rol{l}\t$dst",
|
"rol{l}\t$dst",
|
||||||
[(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
|
[(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
|
||||||
|
def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
|
||||||
|
"rol{q}\t$dst",
|
||||||
|
[(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>;
|
||||||
} // Constraints = "$src = $dst"
|
} // Constraints = "$src = $dst"
|
||||||
|
|
||||||
let Uses = [CL] in {
|
let Uses = [CL] in {
|
||||||
@ -375,17 +468,23 @@ def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
|
|||||||
def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
|
def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
|
||||||
"rol{l}\t{%cl, $dst|$dst, CL}",
|
"rol{l}\t{%cl, $dst|$dst, CL}",
|
||||||
[(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
|
[(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
|
||||||
|
def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst),
|
||||||
|
"rol{q}\t{%cl, $dst|$dst, %CL}",
|
||||||
|
[(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>;
|
||||||
}
|
}
|
||||||
def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
|
def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src1),
|
||||||
"rol{b}\t{$src, $dst|$dst, $src}",
|
"rol{b}\t{$src1, $dst|$dst, $src1}",
|
||||||
[(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
|
[(store (rotl (loadi8 addr:$dst), (i8 imm:$src1)), addr:$dst)]>;
|
||||||
def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
|
def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src1),
|
||||||
"rol{w}\t{$src, $dst|$dst, $src}",
|
"rol{w}\t{$src1, $dst|$dst, $src1}",
|
||||||
[(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
|
[(store (rotl (loadi16 addr:$dst), (i8 imm:$src1)), addr:$dst)]>,
|
||||||
OpSize;
|
OpSize;
|
||||||
def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
|
def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src1),
|
||||||
"rol{l}\t{$src, $dst|$dst, $src}",
|
"rol{l}\t{$src1, $dst|$dst, $src1}",
|
||||||
[(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
|
[(store (rotl (loadi32 addr:$dst), (i8 imm:$src1)), addr:$dst)]>;
|
||||||
|
def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src1),
|
||||||
|
"rol{q}\t{$src1, $dst|$dst, $src1}",
|
||||||
|
[(store (rotl (loadi64 addr:$dst), (i8 imm:$src1)), addr:$dst)]>;
|
||||||
|
|
||||||
// Rotate by 1
|
// Rotate by 1
|
||||||
def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
|
def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
|
||||||
@ -398,6 +497,9 @@ def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
|
|||||||
def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
|
def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
|
||||||
"rol{l}\t$dst",
|
"rol{l}\t$dst",
|
||||||
[(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
|
[(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
|
||||||
|
def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
|
||||||
|
"rol{q}\t$dst",
|
||||||
|
[(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
|
||||||
|
|
||||||
let Constraints = "$src1 = $dst" in {
|
let Constraints = "$src1 = $dst" in {
|
||||||
let Uses = [CL] in {
|
let Uses = [CL] in {
|
||||||
@ -410,6 +512,9 @@ def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
|
|||||||
def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
|
def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
|
||||||
"ror{l}\t{%cl, $dst|$dst, CL}",
|
"ror{l}\t{%cl, $dst|$dst, CL}",
|
||||||
[(set GR32:$dst, (rotr GR32:$src1, CL))]>;
|
[(set GR32:$dst, (rotr GR32:$src1, CL))]>;
|
||||||
|
def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
|
||||||
|
"ror{q}\t{%cl, $dst|$dst, %CL}",
|
||||||
|
[(set GR64:$dst, (rotr GR64:$src1, CL))]>;
|
||||||
}
|
}
|
||||||
|
|
||||||
def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
|
def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
|
||||||
@ -422,6 +527,10 @@ def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
|
|||||||
def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
|
def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
|
||||||
"ror{l}\t{$src2, $dst|$dst, $src2}",
|
"ror{l}\t{$src2, $dst|$dst, $src2}",
|
||||||
[(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
|
[(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
|
||||||
|
def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst),
|
||||||
|
(ins GR64:$src1, i8imm:$src2),
|
||||||
|
"ror{q}\t{$src2, $dst|$dst, $src2}",
|
||||||
|
[(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>;
|
||||||
|
|
||||||
// Rotate by 1
|
// Rotate by 1
|
||||||
def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
|
def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
|
||||||
@ -433,6 +542,9 @@ def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
|
|||||||
def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
|
def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
|
||||||
"ror{l}\t$dst",
|
"ror{l}\t$dst",
|
||||||
[(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
|
[(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
|
||||||
|
def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
|
||||||
|
"ror{q}\t$dst",
|
||||||
|
[(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>;
|
||||||
} // Constraints = "$src = $dst"
|
} // Constraints = "$src = $dst"
|
||||||
|
|
||||||
let Uses = [CL] in {
|
let Uses = [CL] in {
|
||||||
@ -445,6 +557,9 @@ def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
|
|||||||
def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
|
def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
|
||||||
"ror{l}\t{%cl, $dst|$dst, CL}",
|
"ror{l}\t{%cl, $dst|$dst, CL}",
|
||||||
[(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
|
[(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
|
||||||
|
def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
|
||||||
|
"ror{q}\t{%cl, $dst|$dst, %CL}",
|
||||||
|
[(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>;
|
||||||
}
|
}
|
||||||
def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
|
def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
|
||||||
"ror{b}\t{$src, $dst|$dst, $src}",
|
"ror{b}\t{$src, $dst|$dst, $src}",
|
||||||
@ -456,6 +571,9 @@ def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
|
|||||||
def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
|
def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
|
||||||
"ror{l}\t{$src, $dst|$dst, $src}",
|
"ror{l}\t{$src, $dst|$dst, $src}",
|
||||||
[(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
|
[(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
|
||||||
|
def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
|
||||||
|
"ror{q}\t{$src, $dst|$dst, $src}",
|
||||||
|
[(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
|
||||||
|
|
||||||
// Rotate by 1
|
// Rotate by 1
|
||||||
def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
|
def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
|
||||||
@ -468,6 +586,9 @@ def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
|
|||||||
def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
|
def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
|
||||||
"ror{l}\t$dst",
|
"ror{l}\t$dst",
|
||||||
[(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
|
[(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
|
||||||
|
def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
|
||||||
|
"ror{q}\t$dst",
|
||||||
|
[(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
|
||||||
|
|
||||||
|
|
||||||
//===----------------------------------------------------------------------===//
|
//===----------------------------------------------------------------------===//
|
||||||
@ -477,14 +598,6 @@ def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
|
|||||||
let Constraints = "$src1 = $dst" in {
|
let Constraints = "$src1 = $dst" in {
|
||||||
|
|
||||||
let Uses = [CL] in {
|
let Uses = [CL] in {
|
||||||
def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
|
|
||||||
(ins GR32:$src1, GR32:$src2),
|
|
||||||
"shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
|
|
||||||
[(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
|
|
||||||
def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
|
|
||||||
(ins GR32:$src1, GR32:$src2),
|
|
||||||
"shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
|
|
||||||
[(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
|
|
||||||
def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
|
def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
|
||||||
(ins GR16:$src1, GR16:$src2),
|
(ins GR16:$src1, GR16:$src2),
|
||||||
"shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
|
"shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
|
||||||
@ -495,23 +608,27 @@ def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
|
|||||||
"shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
|
"shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
|
||||||
[(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
|
[(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
|
||||||
TB, OpSize;
|
TB, OpSize;
|
||||||
|
def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
|
||||||
|
(ins GR32:$src1, GR32:$src2),
|
||||||
|
"shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
|
||||||
|
[(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
|
||||||
|
def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
|
||||||
|
(ins GR32:$src1, GR32:$src2),
|
||||||
|
"shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
|
||||||
|
[(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
|
||||||
|
def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst),
|
||||||
|
(ins GR64:$src1, GR64:$src2),
|
||||||
|
"shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
|
||||||
|
[(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))]>,
|
||||||
|
TB;
|
||||||
|
def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst),
|
||||||
|
(ins GR64:$src1, GR64:$src2),
|
||||||
|
"shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
|
||||||
|
[(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))]>,
|
||||||
|
TB;
|
||||||
}
|
}
|
||||||
|
|
||||||
let isCommutable = 1 in { // These instructions commute to each other.
|
let isCommutable = 1 in { // These instructions commute to each other.
|
||||||
def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
|
|
||||||
(outs GR32:$dst),
|
|
||||||
(ins GR32:$src1, GR32:$src2, i8imm:$src3),
|
|
||||||
"shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
|
||||||
[(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
|
|
||||||
(i8 imm:$src3)))]>,
|
|
||||||
TB;
|
|
||||||
def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
|
|
||||||
(outs GR32:$dst),
|
|
||||||
(ins GR32:$src1, GR32:$src2, i8imm:$src3),
|
|
||||||
"shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
|
||||||
[(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
|
|
||||||
(i8 imm:$src3)))]>,
|
|
||||||
TB;
|
|
||||||
def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
|
def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
|
||||||
(outs GR16:$dst),
|
(outs GR16:$dst),
|
||||||
(ins GR16:$src1, GR16:$src2, i8imm:$src3),
|
(ins GR16:$src1, GR16:$src2, i8imm:$src3),
|
||||||
@ -526,10 +643,47 @@ def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
|
|||||||
[(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
|
[(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
|
||||||
(i8 imm:$src3)))]>,
|
(i8 imm:$src3)))]>,
|
||||||
TB, OpSize;
|
TB, OpSize;
|
||||||
|
def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
|
||||||
|
(outs GR32:$dst),
|
||||||
|
(ins GR32:$src1, GR32:$src2, i8imm:$src3),
|
||||||
|
"shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
||||||
|
[(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
|
||||||
|
(i8 imm:$src3)))]>,
|
||||||
|
TB;
|
||||||
|
def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
|
||||||
|
(outs GR32:$dst),
|
||||||
|
(ins GR32:$src1, GR32:$src2, i8imm:$src3),
|
||||||
|
"shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
||||||
|
[(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
|
||||||
|
(i8 imm:$src3)))]>,
|
||||||
|
TB;
|
||||||
|
def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
|
||||||
|
(outs GR64:$dst),
|
||||||
|
(ins GR64:$src1, GR64:$src2, i8imm:$src3),
|
||||||
|
"shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
||||||
|
[(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
|
||||||
|
(i8 imm:$src3)))]>,
|
||||||
|
TB;
|
||||||
|
def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
|
||||||
|
(outs GR64:$dst),
|
||||||
|
(ins GR64:$src1, GR64:$src2, i8imm:$src3),
|
||||||
|
"shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
||||||
|
[(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
|
||||||
|
(i8 imm:$src3)))]>,
|
||||||
|
TB;
|
||||||
}
|
}
|
||||||
} // Constraints = "$src = $dst"
|
} // Constraints = "$src = $dst"
|
||||||
|
|
||||||
let Uses = [CL] in {
|
let Uses = [CL] in {
|
||||||
|
def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
|
||||||
|
"shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
|
||||||
|
[(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
|
||||||
|
addr:$dst)]>, TB, OpSize;
|
||||||
|
def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
|
||||||
|
"shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
|
||||||
|
[(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
|
||||||
|
addr:$dst)]>, TB, OpSize;
|
||||||
|
|
||||||
def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
|
def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
|
||||||
"shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
|
"shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
|
||||||
[(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
|
[(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
|
||||||
@ -538,7 +692,30 @@ def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
|
|||||||
"shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
|
"shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
|
||||||
[(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
|
[(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
|
||||||
addr:$dst)]>, TB;
|
addr:$dst)]>, TB;
|
||||||
|
|
||||||
|
def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
|
||||||
|
"shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
|
||||||
|
[(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
|
||||||
|
addr:$dst)]>, TB;
|
||||||
|
def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
|
||||||
|
"shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
|
||||||
|
[(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
|
||||||
|
addr:$dst)]>, TB;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
|
||||||
|
(outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
|
||||||
|
"shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
||||||
|
[(store (X86shld (loadi16 addr:$dst), GR16:$src2,
|
||||||
|
(i8 imm:$src3)), addr:$dst)]>,
|
||||||
|
TB, OpSize;
|
||||||
|
def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
|
||||||
|
(outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
|
||||||
|
"shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
||||||
|
[(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
|
||||||
|
(i8 imm:$src3)), addr:$dst)]>,
|
||||||
|
TB, OpSize;
|
||||||
|
|
||||||
def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
|
def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
|
||||||
(outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
|
(outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
|
||||||
"shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
"shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
||||||
@ -552,27 +729,18 @@ def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
|
|||||||
(i8 imm:$src3)), addr:$dst)]>,
|
(i8 imm:$src3)), addr:$dst)]>,
|
||||||
TB;
|
TB;
|
||||||
|
|
||||||
let Uses = [CL] in {
|
def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
|
||||||
def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
|
(outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
|
||||||
"shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
|
"shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
||||||
[(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
|
[(store (X86shld (loadi64 addr:$dst), GR64:$src2,
|
||||||
addr:$dst)]>, TB, OpSize;
|
(i8 imm:$src3)), addr:$dst)]>,
|
||||||
def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
|
TB;
|
||||||
"shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
|
def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
|
||||||
[(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
|
(outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
|
||||||
addr:$dst)]>, TB, OpSize;
|
"shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
||||||
}
|
[(store (X86shrd (loadi64 addr:$dst), GR64:$src2,
|
||||||
def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
|
(i8 imm:$src3)), addr:$dst)]>,
|
||||||
(outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
|
TB;
|
||||||
"shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
|
||||||
[(store (X86shld (loadi16 addr:$dst), GR16:$src2,
|
|
||||||
(i8 imm:$src3)), addr:$dst)]>,
|
|
||||||
TB, OpSize;
|
|
||||||
def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
|
|
||||||
(outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
|
|
||||||
"shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
|
||||||
[(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
|
|
||||||
(i8 imm:$src3)), addr:$dst)]>,
|
|
||||||
TB, OpSize;
|
|
||||||
} // Defs = [EFLAGS]
|
} // Defs = [EFLAGS]
|
||||||
|
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user