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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-26 07:29:55 +00:00
refactor select 'sched insertion' out to its own method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80764 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -7702,11 +7702,67 @@ X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
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return EndMBB;
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}
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MachineBasicBlock *
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X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
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MachineBasicBlock *BB) const {
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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DebugLoc DL = MI->getDebugLoc();
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// To "insert" a SELECT_CC instruction, we actually have to insert the
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// diamond control-flow pattern. The incoming instruction knows the
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// destination vreg to set, the condition code register to branch on, the
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// true/false values to select between, and a branch opcode to use.
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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MachineFunction::iterator It = BB;
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++It;
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// thisMBB:
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// ...
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// TrueVal = ...
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// cmpTY ccX, r1, r2
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// bCC copy1MBB
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// fallthrough --> copy0MBB
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MachineBasicBlock *thisMBB = BB;
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MachineFunction *F = BB->getParent();
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MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
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unsigned Opc =
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X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
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BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
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F->insert(It, copy0MBB);
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F->insert(It, sinkMBB);
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// Update machine-CFG edges by transferring all successors of the current
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// block to the new block which will contain the Phi node for the select.
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sinkMBB->transferSuccessors(BB);
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// Add the true and fallthrough blocks as its successors.
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BB->addSuccessor(copy0MBB);
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BB->addSuccessor(sinkMBB);
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// copy0MBB:
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// %FalseValue = ...
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// # fallthrough to sinkMBB
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BB = copy0MBB;
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// Update machine-CFG edges
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BB->addSuccessor(sinkMBB);
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// sinkMBB:
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// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
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// ...
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BB = sinkMBB;
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BuildMI(BB, DL, TII->get(X86::PHI), MI->getOperand(0).getReg())
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.addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
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.addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
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F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
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return BB;
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}
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MachineBasicBlock *
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X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *BB) const {
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DebugLoc dl = MI->getDebugLoc();
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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switch (MI->getOpcode()) {
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default: assert(false && "Unexpected instr type to insert");
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case X86::CMOV_GR8:
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@ -7715,57 +7771,8 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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case X86::CMOV_FR64:
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case X86::CMOV_V4F32:
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case X86::CMOV_V2F64:
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case X86::CMOV_V2I64: {
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// To "insert" a SELECT_CC instruction, we actually have to insert the
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// diamond control-flow pattern. The incoming instruction knows the
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// destination vreg to set, the condition code register to branch on, the
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// true/false values to select between, and a branch opcode to use.
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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MachineFunction::iterator It = BB;
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++It;
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// thisMBB:
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// ...
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// TrueVal = ...
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// cmpTY ccX, r1, r2
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// bCC copy1MBB
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// fallthrough --> copy0MBB
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MachineBasicBlock *thisMBB = BB;
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MachineFunction *F = BB->getParent();
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MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
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unsigned Opc =
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X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
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BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
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F->insert(It, copy0MBB);
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F->insert(It, sinkMBB);
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// Update machine-CFG edges by transferring all successors of the current
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// block to the new block which will contain the Phi node for the select.
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sinkMBB->transferSuccessors(BB);
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// Add the true and fallthrough blocks as its successors.
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BB->addSuccessor(copy0MBB);
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BB->addSuccessor(sinkMBB);
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// copy0MBB:
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// %FalseValue = ...
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// # fallthrough to sinkMBB
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BB = copy0MBB;
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// Update machine-CFG edges
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BB->addSuccessor(sinkMBB);
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// sinkMBB:
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// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
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// ...
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BB = sinkMBB;
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BuildMI(BB, dl, TII->get(X86::PHI), MI->getOperand(0).getReg())
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.addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
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.addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
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F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
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return BB;
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}
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case X86::CMOV_V2I64:
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return EmitLoweredSelect(MI, BB);
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case X86::FP32_TO_INT16_IN_MEM:
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case X86::FP32_TO_INT32_IN_MEM:
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@ -7776,27 +7783,30 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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case X86::FP80_TO_INT16_IN_MEM:
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case X86::FP80_TO_INT32_IN_MEM:
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case X86::FP80_TO_INT64_IN_MEM: {
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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DebugLoc DL = MI->getDebugLoc();
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// Change the floating point control register to use "round towards zero"
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// mode when truncating to an integer value.
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MachineFunction *F = BB->getParent();
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int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
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addFrameReference(BuildMI(BB, dl, TII->get(X86::FNSTCW16m)), CWFrameIdx);
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addFrameReference(BuildMI(BB, DL, TII->get(X86::FNSTCW16m)), CWFrameIdx);
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// Load the old value of the high byte of the control word...
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unsigned OldCW =
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F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
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addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16rm), OldCW),
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addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16rm), OldCW),
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CWFrameIdx);
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// Set the high part to be round to zero...
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addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16mi)), CWFrameIdx)
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addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
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.addImm(0xC7F);
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// Reload the modified control word now...
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addFrameReference(BuildMI(BB, dl, TII->get(X86::FLDCW16m)), CWFrameIdx);
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addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
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// Restore the memory image of control word to original value
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addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16mr)), CWFrameIdx)
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addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
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.addReg(OldCW);
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// Get the X86 opcode to use.
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@ -7835,11 +7845,11 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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} else {
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AM.Disp = Op.getImm();
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}
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addFullAddress(BuildMI(BB, dl, TII->get(Opc)), AM)
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addFullAddress(BuildMI(BB, DL, TII->get(Opc)), AM)
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.addReg(MI->getOperand(X86AddrNumOperands).getReg());
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// Reload the original control word now.
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addFrameReference(BuildMI(BB, dl, TII->get(X86::FLDCW16m)), CWFrameIdx);
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addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
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F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
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return BB;
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@ -738,6 +738,9 @@ namespace llvm {
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MachineInstr *BInstr,
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MachineBasicBlock *BB) const;
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MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
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MachineBasicBlock *BB) const;
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/// Emit nodes that will be selected as "test Op0,Op0", or something
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/// equivalent, for use with the given x86 condition code.
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SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG);
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