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Remove a recently redundant transform from X86ISelLowering.

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X86ISelLowering has support to treat:
(icmp ne (and (xor %flags, -1), (shl 1, flag)), 0)

as if it were actually:
(icmp eq (and %flags, (shl 1, flag)), 0)

However, r179386 has code at the InstCombine level to handle this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181145 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
David Majnemer 2013-05-05 02:00:10 +00:00
parent 87defd0924
commit 526f3ed7da
2 changed files with 1 additions and 15 deletions
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11
lib/Target/X86/X86ISelLowering.cpp
View File

@ -9180,14 +9180,6 @@ SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
}
if (LHS.getNode()) {
// If the LHS is of the form (x ^ -1) then replace the LHS with x and flip
// the condition code later.
bool Invert = false;
if (LHS.getOpcode() == ISD::XOR && isAllOnes(LHS.getOperand(1))) {
Invert = true;
LHS = LHS.getOperand(0);
}
// If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
// instruction. Since the shift amount is in-range-or-undefined, we know
// that doing a bittest on the i32 value is ok. We extend to i32 because
@ -9204,9 +9196,6 @@ SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
// Flip the condition if the LHS was a not instruction
if (Invert)
Cond = X86::GetOppositeBranchCondition(Cond);
return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
DAG.getConstant(Cond, MVT::i8), BT);
}

5
test/CodeGen/X86/bt.ll
View File

@ -522,11 +522,8 @@ UnifiedReturnBlock: ; preds = %entry
declare void @foo()
; rdar://12755626
define zeroext i1 @invert(i32 %flags, i32 %flag) nounwind {
; CHECK: invert
; CHECK: btl %eax, %ecx
; CHECK: setae
; CHECK: btl
entry:
%neg = xor i32 %flags, -1
%shl = shl i32 1, %flag