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[FastISel][AArch64] Don't fold the sign-/zero-extend from i1 into the compare.
This fixes a bug I introduced in a previous commit (r216033). Sign-/Zero- extension from i1 cannot be folded into the ADDS/SUBS instructions. Instead both operands have to be sign-/zero-extended with separate instructions. Related to <rdar://problem/17913111>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216073 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -773,19 +773,27 @@ unsigned AArch64FastISel::emitAddsSubs(bool UseAdds, MVT RetVT,
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const Value *LHS, const Value *RHS,
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bool IsZExt, bool WantResult) {
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AArch64_AM::ShiftExtendType ExtendType = AArch64_AM::InvalidShiftExtend;
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MVT SrcVT = RetVT;
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bool NeedExtend = false;
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switch (RetVT.SimpleTy) {
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default: return 0;
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default:
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return 0;
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case MVT::i1:
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NeedExtend = true;
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break;
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case MVT::i8:
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ExtendType = IsZExt ? AArch64_AM::UXTB : AArch64_AM::SXTB; RetVT = MVT::i32;
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NeedExtend = true;
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ExtendType = IsZExt ? AArch64_AM::UXTB : AArch64_AM::SXTB;
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break;
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case MVT::i16:
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ExtendType = IsZExt ? AArch64_AM::UXTH : AArch64_AM::SXTH; RetVT = MVT::i32;
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NeedExtend = true;
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ExtendType = IsZExt ? AArch64_AM::UXTH : AArch64_AM::SXTH;
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break;
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case MVT::i32: // fall-through
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case MVT::i64:
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break;
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case MVT::i32: break;
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case MVT::i64: break;
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}
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MVT SrcVT = RetVT;
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RetVT.SimpleTy = std::max(RetVT.SimpleTy, MVT::i32);
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// Canonicalize immediates to the RHS first.
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if (UseAdds && isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS))
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@ -805,7 +813,7 @@ unsigned AArch64FastISel::emitAddsSubs(bool UseAdds, MVT RetVT,
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return 0;
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bool LHSIsKill = hasTrivialKill(LHS);
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if (ExtendType != AArch64_AM::InvalidShiftExtend)
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if (NeedExtend)
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LHSReg = EmitIntExt(SrcVT, LHSReg, RetVT, IsZExt);
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unsigned ResultReg = 0;
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@ -821,6 +829,7 @@ unsigned AArch64FastISel::emitAddsSubs(bool UseAdds, MVT RetVT,
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if (ResultReg)
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return ResultReg;
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// Only extend the RHS within the instruction if there is a valid extend type.
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if (ExtendType != AArch64_AM::InvalidShiftExtend) {
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if (const auto *SI = dyn_cast<BinaryOperator>(RHS))
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if (const auto *C = dyn_cast<ConstantInt>(SI->getOperand(1)))
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@ -867,6 +876,10 @@ unsigned AArch64FastISel::emitAddsSubs(bool UseAdds, MVT RetVT,
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if (!RHSReg)
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return 0;
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bool RHSIsKill = hasTrivialKill(RHS);
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if (NeedExtend)
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RHSReg = EmitIntExt(SrcVT, RHSReg, RetVT, IsZExt);
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return emitAddsSubs_rr(UseAdds, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill,
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WantResult);
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}
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@ -172,6 +172,17 @@ entry:
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ret i32 %conv2
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}
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define i32 @icmp_i1_signed(i1 %a, i1 %b) nounwind {
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entry:
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; CHECK-LABEL: icmp_i1_signed
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; CHECK: sbfx [[REG1:w[0-9]+]], w0, #0, #1
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; CHECK-NEXT: sbfx [[REG2:w[0-9]+]], w1, #0, #1
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; CHECK-NEXT: cmp [[REG1]], [[REG2]]
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; CHECK-NEXT: cset w0, gt
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%cmp = icmp sgt i1 %a, %b
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%conv2 = zext i1 %cmp to i32
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ret i32 %conv2
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}
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define i32 @icmp_i16_signed_const(i16 %a) nounwind {
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entry:
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