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Rough first pass at compare_and_swap atomic builtins for ARM mode. Work in progress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91090 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
da920fa4f9
commit
5278eb802f
@ -92,6 +92,8 @@ namespace ARMII {
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StMiscFrm = 9 << FormShift,
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LdStMulFrm = 10 << FormShift,
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LdStExFrm = 28 << FormShift,
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// Miscellaneous arithmetic instructions
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ArithMiscFrm = 11 << FormShift,
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@ -3042,6 +3042,77 @@ void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
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// ARM Scheduler Hooks
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//===----------------------------------------------------------------------===//
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MachineBasicBlock *
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ARMTargetLowering::EmitAtomicCmpSwap(unsigned Size, MachineInstr *MI,
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MachineBasicBlock *BB) const {
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unsigned dest = MI->getOperand(0).getReg();
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unsigned ptr = MI->getOperand(1).getReg();
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unsigned oldval = MI->getOperand(2).getReg();
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unsigned newval = MI->getOperand(3).getReg();
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unsigned scratch = BB->getParent()->getRegInfo()
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.createVirtualRegister(ARM::GPRRegisterClass);
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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DebugLoc dl = MI->getDebugLoc();
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unsigned ldrOpc, strOpc;
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switch (Size) {
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default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
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case 1: ldrOpc = ARM::LDREXB; strOpc = ARM::STREXB; break;
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case 2: ldrOpc = ARM::LDREXH; strOpc = ARM::STREXH; break;
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case 4: ldrOpc = ARM::LDREX; strOpc = ARM::STREX; break;
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}
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MachineFunction *MF = BB->getParent();
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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MachineFunction::iterator It = BB;
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++It; // insert the new blocks after the current block
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MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
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MF->insert(It, loop1MBB);
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MF->insert(It, loop2MBB);
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MF->insert(It, exitMBB);
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exitMBB->transferSuccessors(BB);
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// thisMBB:
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// ...
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// fallthrough --> loop1MBB
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BB->addSuccessor(loop1MBB);
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// loop1MBB:
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// ldrex dest, [ptr]
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// cmp dest, oldval
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// bne exitMBB
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BB = loop1MBB;
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AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
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AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::CMPrr))
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.addReg(dest).addReg(oldval));
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BuildMI(BB, dl, TII->get(ARM::Bcc)).addMBB(exitMBB).addImm(ARMCC::NE)
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.addReg(ARM::CPSR);
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BB->addSuccessor(loop2MBB);
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BB->addSuccessor(exitMBB);
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// loop2MBB:
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// strex scratch, newval, [ptr]
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// cmp scratch, #0
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// bne loop1MBB
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BB = loop2MBB;
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AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval)
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.addReg(ptr));
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AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::CMPri))
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.addReg(scratch).addImm(0));
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BuildMI(BB, dl, TII->get(ARM::Bcc)).addMBB(loop1MBB).addImm(ARMCC::NE)
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.addReg(ARM::CPSR);
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BB->addSuccessor(loop1MBB);
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BB->addSuccessor(exitMBB);
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// exitMBB:
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// ...
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BB = exitMBB;
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return BB;
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}
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MachineBasicBlock *
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ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *BB,
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@ -3050,7 +3121,16 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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DebugLoc dl = MI->getDebugLoc();
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switch (MI->getOpcode()) {
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default:
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MI->dump();
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llvm_unreachable("Unexpected instr type to insert");
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case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(1, MI, BB);
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case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(2, MI, BB);
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case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(4, MI, BB);
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case ARM::tMOVCCr_pseudo: {
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// To "insert" a SELECT_CC instruction, we actually have to insert the
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// diamond control-flow pattern. The incoming instruction knows the
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@ -331,6 +331,10 @@ namespace llvm {
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SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
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SDValue &ARMCC, SelectionDAG &DAG, DebugLoc dl);
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MachineBasicBlock *EmitAtomicCmpSwap(unsigned Size, MachineInstr *MI,
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MachineBasicBlock *BB) const;
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};
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}
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@ -33,6 +33,8 @@ def LdMiscFrm : Format<8>;
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def StMiscFrm : Format<9>;
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def LdStMulFrm : Format<10>;
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def LdStExFrm : Format<28>;
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def ArithMiscFrm : Format<11>;
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def ExtFrm : Format<12>;
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@ -264,6 +266,28 @@ class JTI<dag oops, dag iops, InstrItinClass itin,
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: XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm, itin,
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asm, "", pattern>;
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// Atomic load/store instructions
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class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin,
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opc, asm, "", pattern> {
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let Inst{27-23} = 0b00011;
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let Inst{22-21} = opcod;
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let Inst{20} = 1;
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let Inst{11-0} = 0b111110011111;
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}
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class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin,
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opc, asm, "", pattern> {
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let Inst{27-23} = 0b00011;
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let Inst{22-21} = opcod;
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let Inst{20} = 0;
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let Inst{11-0} = 0b111110011111;
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}
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// addrmode1 instructions
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class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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@ -1596,6 +1596,48 @@ def Int_SyncBarrierV7 : AI<(outs), (ins),
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}
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}
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let usesCustomInserter = 1, mayLoad = 1, mayStore = 1 in {
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def ATOMIC_CMP_SWAP_I8 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
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"${:comment} ATOMIC_CMP_SWAP_I8 PSEUDO!",
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[(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
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def ATOMIC_CMP_SWAP_I16 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
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"${:comment} ATOMIC_CMP_SWAP_I16 PSEUDO!",
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[(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
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def ATOMIC_CMP_SWAP_I32 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
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"${:comment} ATOMIC_CMP_SWAP_I32 PSEUDO!",
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[(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
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}
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let mayLoad = 1 in {
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def LDREXB : AIldrex<0b10, (outs GPR:$dest), (ins GPR:$ptr), NoItinerary,
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"ldrexb", "\t$dest, [$ptr]",
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[]>;
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def LDREXH : AIldrex<0b11, (outs GPR:$dest), (ins GPR:$ptr), NoItinerary,
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"ldrexh", "\t$dest, [$ptr]",
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[]>;
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def LDREX : AIldrex<0b00, (outs GPR:$dest), (ins GPR:$ptr), NoItinerary,
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"ldrex", "\t$dest, [$ptr]",
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[]>;
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}
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let mayStore = 1 in {
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def STREXB : AIstrex<0b10, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
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NoItinerary,
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"strexb", "\t$success, $src, [$ptr]",
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[]>;
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def STREXH : AIstrex<0b11, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
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NoItinerary,
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"strexh", "\t$success, $src, [$ptr]",
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[]>;
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def STREX : AIstrex<0b00, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
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NoItinerary,
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"strex", "\t$success, $src, [$ptr]",
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[]>;
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}
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//===----------------------------------------------------------------------===//
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// TLS Instructions
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//
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