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consistency with other cases, no functionality change

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23524 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-09-29 17:38:52 +00:00
parent f13befb456
commit 52897f827e
1 changed files with 2 additions and 0 deletions
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2
lib/Target/PowerPC/PPCISelPattern.cpp
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@ -1058,6 +1058,8 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
DestType = N.getValue(0).getValueType();
if (Result == 1)
Result = ExprMap[N.getValue(0)] = MakeReg(DestType);
else
ExprMap[N.getValue(1)] = 1;
Tmp1 = dyn_cast<RegisterSDNode>(Node->getOperand(1))->getReg();
if (MVT::isInteger(DestType))
BuildMI(BB, PPC::OR, 2, Result).addReg(Tmp1).addReg(Tmp1);