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https://github.com/c64scene-ar/llvm-6502.git
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Annotate a lot of X86InstrInfo.td with SchedRW lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177417 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
parent
023c880220
commit
528c761124
@ -786,7 +786,7 @@ def LEAVE64 : I<0xC9, RawFrm,
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//
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let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
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let mayLoad = 1 in {
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let mayLoad = 1, SchedRW = [WriteLoad] in {
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def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
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IIC_POP_REG16>, OpSize;
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def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
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@ -803,9 +803,9 @@ def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", [],
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def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>, OpSize;
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def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>,
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Requires<[In32BitMode]>;
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}
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} // mayLoad, SchedRW
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let mayStore = 1 in {
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let mayStore = 1, SchedRW = [WriteStore] in {
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def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
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IIC_PUSH_REG>, OpSize;
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def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
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@ -832,29 +832,30 @@ def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>,
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def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>,
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Requires<[In32BitMode]>;
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}
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} // mayStore, SchedRW
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}
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let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
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let mayLoad = 1 in {
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let mayLoad = 1, SchedRW = [WriteLoad] in {
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def POP64r : I<0x58, AddRegFrm,
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(outs GR64:$reg), (ins), "pop{q}\t$reg", [], IIC_POP_REG>;
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def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
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IIC_POP_REG>;
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def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", [],
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IIC_POP_MEM>;
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}
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let mayStore = 1 in {
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} // mayLoad, SchedRW
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let mayStore = 1, SchedRW = [WriteStore] in {
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def PUSH64r : I<0x50, AddRegFrm,
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(outs), (ins GR64:$reg), "push{q}\t$reg", [], IIC_PUSH_REG>;
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def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
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IIC_PUSH_REG>;
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def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [],
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IIC_PUSH_MEM>;
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}
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} // mayStore, SchedRW
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}
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let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
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let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1,
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SchedRW = [WriteStore] in {
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def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
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"push{q}\t$imm", [], IIC_PUSH_IMM>;
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def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
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@ -871,17 +872,18 @@ def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>,
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Requires<[In64BitMode]>;
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let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
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mayLoad=1, neverHasSideEffects=1 in {
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mayLoad = 1, neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
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def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l|d}", [], IIC_POP_A>,
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Requires<[In32BitMode]>;
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}
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let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
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mayStore=1, neverHasSideEffects=1 in {
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mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
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def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l|d}", [], IIC_PUSH_A>,
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Requires<[In32BitMode]>;
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}
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let Constraints = "$src = $dst" in { // GR32 = bswap GR32
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let Constraints = "$src = $dst", SchedRW = [WriteALU] in {
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// GR32 = bswap GR32
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def BSWAP32r : I<0xC8, AddRegFrm,
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(outs GR32:$dst), (ins GR32:$src),
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"bswap{l}\t$dst",
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@ -890,7 +892,7 @@ def BSWAP32r : I<0xC8, AddRegFrm,
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def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
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"bswap{q}\t$dst",
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[(set GR64:$dst, (bswap GR64:$src))], IIC_BSWAP>, TB;
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} // Constraints = "$src = $dst"
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} // Constraints = "$src = $dst", SchedRW
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// Bit scan instructions.
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let Defs = [EFLAGS] in {
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@ -976,7 +978,7 @@ def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", [], IIC_CMPS>;
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//===----------------------------------------------------------------------===//
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// Move Instructions.
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//
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let SchedRW = [WriteMove] in {
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let neverHasSideEffects = 1 in {
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def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
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"mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
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@ -987,6 +989,7 @@ def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
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def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
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"mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
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}
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let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
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def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
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"mov{b}\t{$src, $dst|$dst, $src}",
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@ -1004,7 +1007,9 @@ def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
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"mov{q}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, i64immSExt32:$src)], IIC_MOV>;
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}
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} // SchedRW
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let SchedRW = [WriteStore] in {
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def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
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"mov{b}\t{$src, $dst|$dst, $src}",
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[(store (i8 imm:$src), addr:$dst)], IIC_MOV_MEM>;
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@ -1017,9 +1022,11 @@ def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
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def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
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"mov{q}\t{$src, $dst|$dst, $src}",
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[(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>;
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} // SchedRW
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/// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
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/// 32-bit offset from the PC. These are only valid in x86-32 mode.
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let SchedRW = [WriteALU] in {
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def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
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"mov{b}\t{$src, %al|AL, $src}", [], IIC_MOV_MEM>,
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Requires<[In32BitMode]>;
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@ -1038,6 +1045,7 @@ def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
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def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
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"mov{l}\t{%eax, $dst|$dst, EAX}", [], IIC_MOV_MEM>,
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Requires<[In32BitMode]>;
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}
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// FIXME: These definitions are utterly broken
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// Just leave them commented out for now because they're useless outside
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@ -1055,7 +1063,7 @@ def MOV64ao64 : RIi32<0xA3, RawFrm, (outs offset64:$dst), (ins),
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*/
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let isCodeGenOnly = 1, hasSideEffects = 0 in {
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let isCodeGenOnly = 1, hasSideEffects = 0, SchedRW = [WriteMove] in {
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def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
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"mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
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def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
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@ -1066,7 +1074,7 @@ def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
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"mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
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}
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let canFoldAsLoad = 1, isReMaterializable = 1 in {
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let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
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def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
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"mov{b}\t{$src, $dst|$dst, $src}",
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[(set GR8:$dst, (loadi8 addr:$src))], IIC_MOV_MEM>;
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@ -1081,6 +1089,7 @@ def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
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[(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>;
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}
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let SchedRW = [WriteStore] in {
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def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
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"mov{b}\t{$src, $dst|$dst, $src}",
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[(store GR8:$src, addr:$dst)], IIC_MOV_MEM>;
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@ -1093,6 +1102,7 @@ def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
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def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
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"mov{q}\t{$src, $dst|$dst, $src}",
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[(store GR64:$src, addr:$dst)], IIC_MOV_MEM>;
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} // SchedRW
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// Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
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// that they can be used for copying and storing h registers, which can't be
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@ -1101,34 +1111,37 @@ let isCodeGenOnly = 1 in {
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let neverHasSideEffects = 1 in
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def MOV8rr_NOREX : I<0x88, MRMDestReg,
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(outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
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"mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV>;
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"mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV>,
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Sched<[WriteMove]>;
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let mayStore = 1 in
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def MOV8mr_NOREX : I<0x88, MRMDestMem,
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(outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
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"mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
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IIC_MOV_MEM>;
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IIC_MOV_MEM>, Sched<[WriteStore]>;
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let mayLoad = 1, neverHasSideEffects = 1,
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canFoldAsLoad = 1, isReMaterializable = 1 in
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def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
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(outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
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"mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
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IIC_MOV_MEM>;
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IIC_MOV_MEM>, Sched<[WriteLoad]>;
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}
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// Condition code ops, incl. set if equal/not equal/...
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let SchedRW = [WriteALU] in {
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let Defs = [EFLAGS], Uses = [AH] in
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def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf",
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[(set EFLAGS, (X86sahf AH))], IIC_AHF>;
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let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
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def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [],
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IIC_AHF>; // AH = flags
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} // SchedRW
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//===----------------------------------------------------------------------===//
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// Bit tests instructions: BT, BTS, BTR, BTC.
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let Defs = [EFLAGS] in {
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let SchedRW = [WriteALU] in {
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def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
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"bt{w}\t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))], IIC_BT_RR>,
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@ -1139,13 +1152,14 @@ def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
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def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
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"bt{q}\t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB;
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} // SchedRW
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// Unlike with the register+register form, the memory+register form of the
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// bt instruction does not ignore the high bits of the index. From ISel's
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// perspective, this is pretty bizarre. Make these instructions disassembly
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// only for now.
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let mayLoad = 1, hasSideEffects = 0 in {
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let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteALULd] in {
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def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
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"bt{w}\t{$src2, $src1|$src1, $src2}",
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// [(X86bt (loadi16 addr:$src1), GR16:$src2),
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@ -1166,6 +1180,7 @@ let mayLoad = 1, hasSideEffects = 0 in {
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>, TB;
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}
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let SchedRW = [WriteALU] in {
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def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
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"bt{w}\t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))],
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@ -1178,10 +1193,12 @@ def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
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"bt{q}\t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))],
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IIC_BT_RI>, TB;
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} // SchedRW
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// Note that these instructions don't need FastBTMem because that
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// only applies when the other operand is in a register. When it's
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// an immediate, bt is still fast.
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let SchedRW = [WriteALU] in {
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def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
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"bt{w}\t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
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@ -1194,8 +1211,10 @@ def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
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"bt{q}\t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86bt (loadi64 addr:$src1),
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i64immSExt8:$src2))], IIC_BT_MI>, TB;
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} // SchedRW
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let hasSideEffects = 0 in {
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let SchedRW = [WriteALU] in {
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def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
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"btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
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OpSize, TB;
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@ -1203,8 +1222,9 @@ def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
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"btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
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def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
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"btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
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} // SchedRW
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let mayLoad = 1, mayStore = 1 in {
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let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd] in {
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def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
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"btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
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OpSize, TB;
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@ -1214,6 +1234,7 @@ def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
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"btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
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}
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let SchedRW = [WriteALU] in {
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def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
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"btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
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OpSize, TB;
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@ -1221,8 +1242,9 @@ def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
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"btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
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def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
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"btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
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} // SchedRW
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let mayLoad = 1, mayStore = 1 in {
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let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
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def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
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"btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
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OpSize, TB;
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@ -1232,6 +1254,7 @@ def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
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"btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
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}
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let SchedRW = [WriteALU] in {
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def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
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"btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
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OpSize, TB;
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@ -1239,6 +1262,7 @@ def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
|
||||
"btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
|
||||
def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
|
||||
"btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
||||
} // SchedRW
|
||||
|
||||
let mayLoad = 1, mayStore = 1 in {
|
||||
def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
|
||||
@ -1250,6 +1274,7 @@ def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
|
||||
"btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
|
||||
}
|
||||
|
||||
let SchedRW = [WriteALU] in {
|
||||
def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
|
||||
"btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
|
||||
OpSize, TB;
|
||||
@ -1257,8 +1282,9 @@ def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
|
||||
"btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
|
||||
def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
|
||||
"btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
|
||||
} // SchedRW
|
||||
|
||||
let mayLoad = 1, mayStore = 1 in {
|
||||
let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
|
||||
def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
|
||||
"btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
|
||||
OpSize, TB;
|
||||
@ -1268,6 +1294,7 @@ def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
|
||||
"btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
|
||||
}
|
||||
|
||||
let SchedRW = [WriteALU] in {
|
||||
def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
|
||||
"bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
|
||||
OpSize, TB;
|
||||
@ -1275,8 +1302,9 @@ def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
|
||||
"bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
|
||||
def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
|
||||
"bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
|
||||
} // SchedRW
|
||||
|
||||
let mayLoad = 1, mayStore = 1 in {
|
||||
let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
|
||||
def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
|
||||
"bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
|
||||
OpSize, TB;
|
||||
@ -1286,6 +1314,7 @@ def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
|
||||
"bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
|
||||
}
|
||||
|
||||
let SchedRW = [WriteALU] in {
|
||||
def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
|
||||
"bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
|
||||
OpSize, TB;
|
||||
@ -1293,8 +1322,9 @@ def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
|
||||
"bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
|
||||
def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
|
||||
"bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
|
||||
} // SchedRW
|
||||
|
||||
let mayLoad = 1, mayStore = 1 in {
|
||||
let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
|
||||
def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
|
||||
"bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
|
||||
OpSize, TB;
|
||||
@ -1533,6 +1563,7 @@ def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
|
||||
// MOVBE Instructions
|
||||
//
|
||||
let Predicates = [HasMOVBE] in {
|
||||
let SchedRW = [WriteALULd] in {
|
||||
def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
|
||||
"movbe{w}\t{$src, $dst|$dst, $src}",
|
||||
[(set GR16:$dst, (bswap (loadi16 addr:$src)))], IIC_MOVBE>,
|
||||
@ -1545,6 +1576,8 @@ let Predicates = [HasMOVBE] in {
|
||||
"movbe{q}\t{$src, $dst|$dst, $src}",
|
||||
[(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>,
|
||||
T8;
|
||||
}
|
||||
let SchedRW = [WriteStore] in {
|
||||
def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
|
||||
"movbe{w}\t{$src, $dst|$dst, $src}",
|
||||
[(store (bswap GR16:$src), addr:$dst)], IIC_MOVBE>,
|
||||
@ -1557,6 +1590,7 @@ let Predicates = [HasMOVBE] in {
|
||||
"movbe{q}\t{$src, $dst|$dst, $src}",
|
||||
[(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>,
|
||||
T8;
|
||||
}
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
Loading…
Reference in New Issue
Block a user