From 52b072d73fb8ee269e20a97fd3fcf59b4313e2f0 Mon Sep 17 00:00:00 2001
From: Chandler Carruth <chandlerc@gmail.com>
Date: Tue, 30 Sep 2014 02:32:36 +0000
Subject: [PATCH] [x86] Add some vector-register broadcast operations to the
 256-bit v4 tests which were missing them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218657 91177308-0d34-0410-b5e6-96231b3b80d8
---
 test/CodeGen/X86/vector-shuffle-256-v4.ll | 30 +++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/test/CodeGen/X86/vector-shuffle-256-v4.ll b/test/CodeGen/X86/vector-shuffle-256-v4.ll
index b7cfa0b1dab..717c7cddba7 100644
--- a/test/CodeGen/X86/vector-shuffle-256-v4.ll
+++ b/test/CodeGen/X86/vector-shuffle-256-v4.ll
@@ -3,6 +3,21 @@
 
 target triple = "x86_64-unknown-unknown"
 
+define <4 x double> @shuffle_v4f64_0000(<4 x double> %a, <4 x double> %b) {
+; AVX1-LABEL: @shuffle_v4f64_0000
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vunpcklpd {{.*}} # xmm0 = xmm0[0,0]
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: @shuffle_v4f64_0000
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpermpd {{.*}} # ymm0 = ymm0[0,0,0,0]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
+  ret <4 x double> %shuffle
+}
+
 define <4 x double> @shuffle_v4f64_0001(<4 x double> %a, <4 x double> %b) {
 ; AVX1-LABEL: @shuffle_v4f64_0001
 ; AVX1:       # BB#0:
@@ -293,6 +308,21 @@ define <4 x double> @shuffle_v4f64_0167(<4 x double> %a, <4 x double> %b) {
   ret <4 x double> %shuffle
 }
 
+define <4 x i64> @shuffle_v4i64_0000(<4 x i64> %a, <4 x i64> %b) {
+; AVX1-LABEL: @shuffle_v4i64_0000
+; AVX1:       # BB#0:
+; AVX1-NEXT:    vunpcklpd {{.*}} # xmm0 = xmm0[0,0]
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: @shuffle_v4i64_0000
+; AVX2:       # BB#0:
+; AVX2-NEXT:    vpermq {{.*}} # ymm0 = ymm0[0,0,0,0]
+; AVX2-NEXT:    retq
+  %shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
+  ret <4 x i64> %shuffle
+}
+
 define <4 x i64> @shuffle_v4i64_0001(<4 x i64> %a, <4 x i64> %b) {
 ; AVX1-LABEL: @shuffle_v4i64_0001
 ; AVX1:       # BB#0: