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Use precomputed BitVector for CodeGenRegisterClass::hasSubClass().

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All the sub-class bit vectors are computed when first creating the
register bank.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140905 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2011-09-30 23:47:05 +00:00
parent 0676d2a04c
commit 52e7dfadc6
2 changed files with 15 additions and 8 deletions
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15
utils/TableGen/CodeGenRegisters.cpp
View File

@ -342,11 +342,12 @@ bool CodeGenRegisterClass::contains(const CodeGenRegister *Reg) const {
// 2. The RC spill size must not be smaller than our spill size.
// 3. RC spill alignment must be compatible with ours.
//
bool CodeGenRegisterClass::hasSubClass(const CodeGenRegisterClass *RC) const {
return SpillAlignment && RC->SpillAlignment % SpillAlignment == 0 &&
SpillSize <= RC->SpillSize &&
std::includes(Members.begin(), Members.end(),
RC->Members.begin(), RC->Members.end(),
static bool testSubClass(const CodeGenRegisterClass *A,
const CodeGenRegisterClass *B) {
return A->SpillAlignment && B->SpillAlignment % A->SpillAlignment == 0 &&
A->SpillSize <= B->SpillSize &&
std::includes(A->getMembers().begin(), A->getMembers().end(),
B->getMembers().begin(), B->getMembers().end(),
CodeGenRegister::Less());
}
@ -403,7 +404,7 @@ computeSubClasses(ArrayRef<CodeGenRegisterClass*> RegClasses) {
if (RC.SubClasses.test(s))
continue;
CodeGenRegisterClass *SubRC = RegClasses[s];
if (!RC.hasSubClass(SubRC))
if (!testSubClass(&RC, SubRC))
continue;
// SubRC is a sub-class. Grap all its sub-classes so we won't have to
// check them again.
@ -411,7 +412,7 @@ computeSubClasses(ArrayRef<CodeGenRegisterClass*> RegClasses) {
}
// Sweep up missed clique members. They will be immediately preceeding RC.
for (unsigned s = rci - 1; s && RC.hasSubClass(RegClasses[s - 1]); --s)
for (unsigned s = rci - 1; s && testSubClass(&RC, RegClasses[s - 1]); --s)
RC.SubClasses.set(s - 1);
}

8
utils/TableGen/CodeGenRegisters.h
View File

@ -129,7 +129,9 @@ namespace llvm {
// 2. The RC spill size must not be smaller than our spill size.
// 3. RC spill alignment must be compatible with ours.
//
bool hasSubClass(const CodeGenRegisterClass *RC) const;
bool hasSubClass(const CodeGenRegisterClass *RC) const {
return SubClasses.test(RC->EnumValue);
}
// getSubClasses - Returns a constant BitVector of subclasses indexed by
// EnumValue.
@ -155,6 +157,10 @@ namespace llvm {
// Return the total number of allocation orders available.
unsigned getNumOrders() const { return 1 + AltOrders.size(); }
// Get the set of registers. This set contains the same registers as
// getOrder(0).
const CodeGenRegister::Set &getMembers() const { return Members; }
CodeGenRegisterClass(CodeGenRegBank&, Record *R);
// Called by CodeGenRegBank::CodeGenRegBank().