diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
index d3caca624df..c28f7e12efb 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
@@ -1098,10 +1098,11 @@ static bool DisassembleLdStFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
       OpIdx += 1;
     }
 
-    // Disassemble the 12-bit immediate offset.
+    // Disassemble the 12-bit immediate offset, which is the second operand in
+    // $addrmode_imm12 => (ops GPR:$base, i32imm:$offsimm).
+    // 
     unsigned Imm12 = slice(insn, 11, 0);
-    unsigned Offset = ARM_AM::getAM2Opc(AddrOpcode, Imm12, ARM_AM::no_shift,
-                                        IndexMode);
+    int Offset = AddrOpcode == ARM_AM::add ? 1 * Imm12 : -1 * Imm12;
     MI.addOperand(MCOperand::CreateImm(Offset));
     OpIdx += 1;
   } else {
diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt
index f10dea20227..7947c6a3d59 100644
--- a/test/MC/Disassembler/ARM/arm-tests.txt
+++ b/test/MC/Disassembler/ARM/arm-tests.txt
@@ -164,6 +164,15 @@
 # CHECK:	ldr	r3, [pc, #144]
 0x90 0x30 0x9f 0xe5
 
+# CHECK:	ldr	r3, [r0, #-4]
+0x4 0x30 0x10 0xe5
+
+# CHECK:	ldr	r5, [sp, r0, lsl #1]!
+0x80 0x50 0xbd 0xe7
+
+# CHECK:	ldr	r5, [r7], -r0, lsr #2
+0x20 0x51 0x17 0xe6
+
 # CHECK:	strdeq	r2, r3, [r0], -r8
 0xf8 0x24 0x00 0x00