mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-17 05:29:24 +00:00
Two bug fixes:
(1) Add edges for Values that are written by multiple m/c instructions (2) Add edges for LLVM operands that are not machine operands (e.g., Call args) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@676 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
aca997cbd7
commit
5316f8fa2f
@ -23,6 +23,18 @@
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#include "llvm/Support/StringExtras.h"
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#include <algorithm>
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//*********************** Internal Data Structures *************************/
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typedef vector< pair<SchedGraphNode*, unsigned int> > RefVec;
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// The following needs to be a class, not a typedef, so we can use
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// an opaque declaration in SchedGraph.h
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class RegToRefVecMap: public hash_map<int, RefVec> {
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typedef hash_map<int, RefVec>:: iterator iterator;
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typedef hash_map<int, RefVec>::const_iterator const_iterator;
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};
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//
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// class SchedGraphEdge
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//
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@ -46,11 +58,11 @@ SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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/*ctor*/
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SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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SchedGraphNode* _sink,
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Value* _val,
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SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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SchedGraphNode* _sink,
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const Value* _val,
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DataDepOrderType _depOrderType,
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int _minDelay)
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int _minDelay)
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: src(_src),
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sink(_sink),
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depType(DefUseDep),
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@ -64,11 +76,11 @@ SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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/*ctor*/
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SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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SchedGraphNode* _sink,
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unsigned int _regNum,
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SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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SchedGraphNode* _sink,
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unsigned int _regNum,
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DataDepOrderType _depOrderType,
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int _minDelay)
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int _minDelay)
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: src(_src),
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sink(_sink),
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depType(MachineRegister),
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@ -85,7 +97,7 @@ SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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SchedGraphNode* _sink,
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ResourceId _resourceId,
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int _minDelay)
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int _minDelay)
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: src(_src),
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sink(_sink),
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depType(MachineResource),
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@ -467,18 +479,8 @@ SchedGraph::addMemEdges(const vector<const Instruction*>& memVec,
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}
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typedef vector< pair<SchedGraphNode*, unsigned int> > RegRefVec;
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// The following needs to be a class, not a typedef, so we can use
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// an opaque declaration in SchedGraph.h
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class NodeToRegRefMap: public hash_map<int, RegRefVec> {
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typedef hash_map<int, RegRefVec>:: iterator iterator;
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typedef hash_map<int, RegRefVec>::const_iterator const_iterator;
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};
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void
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SchedGraph::addMachineRegEdges(NodeToRegRefMap& regToRefVecMap,
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SchedGraph::addMachineRegEdges(RegToRefVecMap& regToRefVecMap,
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const TargetMachine& target)
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{
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assert(bbVec.size() == 1 && "Only handling a single basic block here");
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@ -489,49 +491,49 @@ SchedGraph::addMachineRegEdges(NodeToRegRefMap& regToRefVecMap,
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// Also assumes that two registers with different numbers are
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// not aliased!
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//
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for (NodeToRegRefMap::iterator I = regToRefVecMap.begin();
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for (RegToRefVecMap::iterator I = regToRefVecMap.begin();
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I != regToRefVecMap.end(); ++I)
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{
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int regNum = (*I).first;
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RegRefVec& regRefVec = (*I).second;
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int regNum = (*I).first;
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RefVec& regRefVec = (*I).second;
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// regRefVec is ordered by control flow order in the basic block
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int lastDefIdx = -1;
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for (unsigned i=0; i < regRefVec.size(); ++i)
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{
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SchedGraphNode* node = regRefVec[i].first;
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bool isDef = regRefVec[i].second;
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if (isDef)
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{ // Each def gets an output edge from the last def
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if (lastDefIdx > 0)
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new SchedGraphEdge(regRefVec[lastDefIdx].first, node, regNum,
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SchedGraphEdge::OutputDep);
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// Also, an anti edge from all uses *since* the last def,
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// But don't add edge from an instruction to itself!
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for (int u = 1 + lastDefIdx; u < (int) i; u++)
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if (regRefVec[u].first != node)
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new SchedGraphEdge(regRefVec[u].first, node, regNum,
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SchedGraphEdge::AntiDep);
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}
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else
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{ // Each use gets a true edge from the last def
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if (lastDefIdx > 0)
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new SchedGraphEdge(regRefVec[lastDefIdx].first, node, regNum);
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}
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}
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unsigned int opNum = regRefVec[i].second;
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bool isDef = node->getMachineInstr()->operandIsDefined(opNum);
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for (unsigned p=0; p < i; ++p)
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{
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SchedGraphNode* prevNode = regRefVec[p].first;
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if (prevNode != node)
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{
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unsigned int prevOpNum = regRefVec[p].second;
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bool prevIsDef =
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prevNode->getMachineInstr()->operandIsDefined(prevOpNum);
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if (isDef)
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new SchedGraphEdge(prevNode, node, regNum,
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(prevIsDef)? SchedGraphEdge::OutputDep
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: SchedGraphEdge::AntiDep);
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else if (prevIsDef)
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new SchedGraphEdge(prevNode, node, regNum,
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SchedGraphEdge::TrueDep);
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}
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}
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}
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}
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}
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void
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SchedGraph::addSSAEdge(SchedGraphNode* node,
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Value* val,
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const Value* val,
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const TargetMachine& target)
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{
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if (!val->isInstruction()) return;
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const Instruction* thisVMInstr = node->getInstr();
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const Instruction* defVMInstr = val->castInstructionAsserting();
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@ -562,38 +564,38 @@ SchedGraph::addSSAEdge(SchedGraphNode* node,
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// if there is a node for it in the same graph, add an edge.
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SchedGraphNode* defNode = this->getGraphNodeForInstr(defMvec[i]);
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if (defNode != NULL && defNode != node)
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(void) new SchedGraphEdge(defNode, node, val);
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(void) new SchedGraphEdge(defNode, node, val);
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}
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}
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}
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void
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SchedGraph::addEdgesForInstruction(SchedGraphNode* node,
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NodeToRegRefMap& regToRefVecMap,
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SchedGraph::addEdgesForInstruction(const MachineInstr& minstr,
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RegToRefVecMap& regToRefVecMap,
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const TargetMachine& target)
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{
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const Instruction& instr = * node->getInstr(); // No dummy nodes here!
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const MachineInstr& minstr = * node->getMachineInstr();
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SchedGraphNode* node = this->getGraphNodeForInstr(&minstr);
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if (node == NULL)
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return;
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// Add incoming edges for the following:
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// (1) operands of the machine instruction, including hidden operands
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// (2) machine register dependences
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// (3) other resource dependences for the machine instruction, if any
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// Also, note any uses or defs of machine registers.
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assert(node->getInstr() && "Should be no dummy nodes here!");
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const Instruction& instr = * node->getInstr();
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// Add edges for all operands of the machine instruction.
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// Also, record all machine register references to add reg. deps. later.
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//
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for (unsigned i=0, numOps=minstr.getNumOperands(); i < numOps; i++)
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{
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const MachineOperand& mop = minstr.getOperand(i);
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// if this writes to a machine register other than the hardwired
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// "zero" register used on many processors, record the reference.
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// "zero" register, record the reference.
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if (mop.getOperandType() == MachineOperand::MO_MachineRegister
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&& (mop.getMachineRegNum()
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== (unsigned) target.getRegInfo().getZeroRegNum()))
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!= (unsigned) target.getRegInfo().getZeroRegNum()))
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{
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regToRefVecMap[mop.getMachineRegNum()].
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push_back(make_pair(node, i));
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regToRefVecMap[mop.getMachineRegNum()].push_back(make_pair(node, i));
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}
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// ignore all other def operands
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@ -621,10 +623,87 @@ SchedGraph::addEdgesForInstruction(SchedGraphNode* node,
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break;
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}
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}
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// add all true, anti,
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// and output dependences for this register. but ignore
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// Add edges for values implicitly used by the machine instruction sequence
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// for the VM instruction but not made explicit operands. Examples include
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// function arguments to a Call instructions or the return value of a Ret
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// instruction. We'll conservatively add the dependences to every machine
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// machine instruction in the instruction sequence for this VM instr
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// (at least for now, there is never more than one machine instr).
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//
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const vector<const Value*>& implicitUses =
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instr.getMachineInstrVec().getImplicitUses();
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for (unsigned i=0; i < implicitUses.size(); ++i)
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addSSAEdge(node, implicitUses[i], target);
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}
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void
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SchedGraph::addNonSSAEdgesForValue(const Instruction* instr,
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const TargetMachine& target)
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{
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assert(instr->isInstruction());
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if (instr->isPHINode())
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return;
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MachineCodeForVMInstr& mvec = instr->getMachineInstrVec();
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const MachineInstrInfo& mii = target.getInstrInfo();
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RefVec refVec;
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for (unsigned i=0, N=mvec.size(); i < N; i++)
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for (int o=0, N = mii.getNumOperands(mvec[i]->getOpCode()); o < N; o++)
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{
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const MachineOperand& op = mvec[i]->getOperand(o);
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if ((op.getOperandType() == MachineOperand::MO_VirtualRegister ||
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op.getOperandType() == MachineOperand::MO_CCRegister)
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&& op.getVRegValue() == (Value*) instr)
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{
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// this operand is a definition or use of value `instr'
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SchedGraphNode* node = this->getGraphNodeForInstr(mvec[i]);
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assert(node && "No node for machine instruction in this BB?");
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refVec.push_back(make_pair(node, o));
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}
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}
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// refVec is ordered by control flow order of the machine instructions
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for (unsigned i=0; i < refVec.size(); ++i)
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{
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SchedGraphNode* node = refVec[i].first;
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unsigned int opNum = refVec[i].second;
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bool isDef = node->getMachineInstr()->operandIsDefined(opNum);
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if (isDef)
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// add output and/or anti deps to this definition
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for (unsigned p=0; p < i; ++p)
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{
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SchedGraphNode* prevNode = refVec[p].first;
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if (prevNode != node)
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{
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bool prevIsDef = prevNode->getMachineInstr()->
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operandIsDefined(refVec[p].second);
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new SchedGraphEdge(prevNode, node, SchedGraphEdge::DefUseDep,
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(prevIsDef)? SchedGraphEdge::OutputDep
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: SchedGraphEdge::AntiDep);
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}
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}
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}
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}
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void
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SchedGraph::buildNodesforVMInstr(const TargetMachine& target,
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const Instruction* instr)
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{
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const MachineInstrInfo& mii = target.getInstrInfo();
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const MachineCodeForVMInstr& mvec = instr->getMachineInstrVec();
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for (unsigned i=0; i < mvec.size(); i++)
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if (! mii.isDummyPhiInstr(mvec[i]->getOpCode()))
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{
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SchedGraphNode* node = new SchedGraphNode(getNumNodes(),
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instr, mvec[i], target);
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this->noteGraphNodeForInstr(mvec[i], node);
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}
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}
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@ -649,37 +728,46 @@ SchedGraph::buildGraph(const TargetMachine& target)
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// single basic block, hence the assertion. Each reference is identified
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// by the pair: <node, operand-number>.
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//
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NodeToRegRefMap regToRefVecMap;
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RegToRefVecMap regToRefVecMap;
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// Make a dummy root node. We'll add edges to the real roots later.
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graphRoot = new SchedGraphNode(0, NULL, NULL, target);
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graphLeaf = new SchedGraphNode(1, NULL, NULL, target);
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//----------------------------------------------------------------
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// First add nodes for all the machine instructions in the basic block.
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// This greatly simplifies identifing which edges to add.
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// First add nodes for all the machine instructions in the basic block
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// because this greatly simplifies identifying which edges to add.
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// Do this one VM instruction at a time since the SchedGraphNode needs that.
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// Also, remember the load/store instructions to add memory deps later.
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//----------------------------------------------------------------
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for (BasicBlock::const_iterator II = bb->begin(); II != bb->end(); ++II)
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{
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const Instruction *instr = *II;
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const MachineCodeForVMInstr& mvec = instr->getMachineInstrVec();
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for (unsigned i=0, N=mvec.size(); i < N; i++)
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if (! mii.isDummyPhiInstr(mvec[i]->getOpCode()))
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{
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SchedGraphNode* node = new SchedGraphNode(getNumNodes(),
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instr, mvec[i], target);
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this->noteGraphNodeForInstr(mvec[i], node);
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}
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// Build graph nodes for this VM instruction
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buildNodesforVMInstr(target, instr);
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// Remember the load/store instructions to add memory deps later.
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if (instr->getOpcode() == Instruction::Load ||
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instr->getOpcode() == Instruction::Store)
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memVec.push_back(instr);
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}
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//----------------------------------------------------------------
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// Now add the edges.
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// Now add edges for the following (all are incoming edges except (4)):
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// (1) operands of the machine instruction, including hidden operands
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// (2) machine register dependences
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// (3) memory load/store dependences
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// (3) other resource dependences for the machine instruction, if any
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// (4) output dependences when multiple machine instructions define the
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// same value; all must have been generated from a single VM instrn
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// (5) control dependences to branch instructions generated for the
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// terminator instruction of the BB. Because of delay slots and
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// 2-way conditional branches, multiple CD edges are needed
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// (see addCDEdges for details).
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// Also, note any uses or defs of machine registers.
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//
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//----------------------------------------------------------------
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// First, add edges to the terminator instruction of the basic block.
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@ -689,10 +777,21 @@ SchedGraph::buildGraph(const TargetMachine& target)
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this->addMemEdges(memVec, target);
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// Then add other edges for all instructions in the block.
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for (SchedGraph::iterator GI = this->begin(); GI != this->end(); ++GI)
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// Do this in machine code order and find all references to machine regs.
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MachineCodeForBasicBlock& mvec = bb->getMachineInstrVec();
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for (unsigned i=0, N=mvec.size(); i < N; i++)
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addEdgesForInstruction(*mvec[i], regToRefVecMap, target);
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// Since the code is no longer in SSA form, add output dep. edges
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// between machine instructions that define the same Value, and anti-dep.
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// edges from those to other machine instructions for the same VM instr.
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// We assume that all machine instructions that define a value are
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// generated from the VM instruction corresponding to that value.
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//
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for (BasicBlock::const_iterator II = bb->begin(); II != bb->end(); ++II)
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{
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SchedGraphNode* node = (*GI).second;
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addEdgesForInstruction(node, regToRefVecMap, target);
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const Instruction *instr = *II;
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this->addNonSSAEdgesForValue(instr, target);
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}
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// Then add edges for dependences on machine registers
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@ -23,6 +23,18 @@
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#include "llvm/Support/StringExtras.h"
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#include <algorithm>
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//*********************** Internal Data Structures *************************/
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typedef vector< pair<SchedGraphNode*, unsigned int> > RefVec;
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// The following needs to be a class, not a typedef, so we can use
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// an opaque declaration in SchedGraph.h
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class RegToRefVecMap: public hash_map<int, RefVec> {
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typedef hash_map<int, RefVec>:: iterator iterator;
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typedef hash_map<int, RefVec>::const_iterator const_iterator;
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};
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//
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// class SchedGraphEdge
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//
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@ -46,11 +58,11 @@ SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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/*ctor*/
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SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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SchedGraphNode* _sink,
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Value* _val,
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SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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SchedGraphNode* _sink,
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const Value* _val,
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DataDepOrderType _depOrderType,
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int _minDelay)
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int _minDelay)
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: src(_src),
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sink(_sink),
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depType(DefUseDep),
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@ -64,11 +76,11 @@ SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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/*ctor*/
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SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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SchedGraphNode* _sink,
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unsigned int _regNum,
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SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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SchedGraphNode* _sink,
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unsigned int _regNum,
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DataDepOrderType _depOrderType,
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int _minDelay)
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int _minDelay)
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: src(_src),
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sink(_sink),
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depType(MachineRegister),
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@ -85,7 +97,7 @@ SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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SchedGraphNode* _sink,
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ResourceId _resourceId,
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int _minDelay)
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int _minDelay)
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: src(_src),
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sink(_sink),
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depType(MachineResource),
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@ -467,18 +479,8 @@ SchedGraph::addMemEdges(const vector<const Instruction*>& memVec,
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}
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typedef vector< pair<SchedGraphNode*, unsigned int> > RegRefVec;
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// The following needs to be a class, not a typedef, so we can use
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// an opaque declaration in SchedGraph.h
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class NodeToRegRefMap: public hash_map<int, RegRefVec> {
|
||||
typedef hash_map<int, RegRefVec>:: iterator iterator;
|
||||
typedef hash_map<int, RegRefVec>::const_iterator const_iterator;
|
||||
};
|
||||
|
||||
|
||||
void
|
||||
SchedGraph::addMachineRegEdges(NodeToRegRefMap& regToRefVecMap,
|
||||
SchedGraph::addMachineRegEdges(RegToRefVecMap& regToRefVecMap,
|
||||
const TargetMachine& target)
|
||||
{
|
||||
assert(bbVec.size() == 1 && "Only handling a single basic block here");
|
||||
@ -489,49 +491,49 @@ SchedGraph::addMachineRegEdges(NodeToRegRefMap& regToRefVecMap,
|
||||
// Also assumes that two registers with different numbers are
|
||||
// not aliased!
|
||||
//
|
||||
for (NodeToRegRefMap::iterator I = regToRefVecMap.begin();
|
||||
for (RegToRefVecMap::iterator I = regToRefVecMap.begin();
|
||||
I != regToRefVecMap.end(); ++I)
|
||||
{
|
||||
int regNum = (*I).first;
|
||||
RegRefVec& regRefVec = (*I).second;
|
||||
int regNum = (*I).first;
|
||||
RefVec& regRefVec = (*I).second;
|
||||
|
||||
// regRefVec is ordered by control flow order in the basic block
|
||||
int lastDefIdx = -1;
|
||||
for (unsigned i=0; i < regRefVec.size(); ++i)
|
||||
{
|
||||
SchedGraphNode* node = regRefVec[i].first;
|
||||
bool isDef = regRefVec[i].second;
|
||||
|
||||
if (isDef)
|
||||
{ // Each def gets an output edge from the last def
|
||||
if (lastDefIdx > 0)
|
||||
new SchedGraphEdge(regRefVec[lastDefIdx].first, node, regNum,
|
||||
SchedGraphEdge::OutputDep);
|
||||
|
||||
// Also, an anti edge from all uses *since* the last def,
|
||||
// But don't add edge from an instruction to itself!
|
||||
for (int u = 1 + lastDefIdx; u < (int) i; u++)
|
||||
if (regRefVec[u].first != node)
|
||||
new SchedGraphEdge(regRefVec[u].first, node, regNum,
|
||||
SchedGraphEdge::AntiDep);
|
||||
}
|
||||
else
|
||||
{ // Each use gets a true edge from the last def
|
||||
if (lastDefIdx > 0)
|
||||
new SchedGraphEdge(regRefVec[lastDefIdx].first, node, regNum);
|
||||
}
|
||||
}
|
||||
unsigned int opNum = regRefVec[i].second;
|
||||
bool isDef = node->getMachineInstr()->operandIsDefined(opNum);
|
||||
|
||||
for (unsigned p=0; p < i; ++p)
|
||||
{
|
||||
SchedGraphNode* prevNode = regRefVec[p].first;
|
||||
if (prevNode != node)
|
||||
{
|
||||
unsigned int prevOpNum = regRefVec[p].second;
|
||||
bool prevIsDef =
|
||||
prevNode->getMachineInstr()->operandIsDefined(prevOpNum);
|
||||
|
||||
if (isDef)
|
||||
new SchedGraphEdge(prevNode, node, regNum,
|
||||
(prevIsDef)? SchedGraphEdge::OutputDep
|
||||
: SchedGraphEdge::AntiDep);
|
||||
else if (prevIsDef)
|
||||
new SchedGraphEdge(prevNode, node, regNum,
|
||||
SchedGraphEdge::TrueDep);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
SchedGraph::addSSAEdge(SchedGraphNode* node,
|
||||
Value* val,
|
||||
const Value* val,
|
||||
const TargetMachine& target)
|
||||
{
|
||||
if (!val->isInstruction()) return;
|
||||
|
||||
|
||||
const Instruction* thisVMInstr = node->getInstr();
|
||||
const Instruction* defVMInstr = val->castInstructionAsserting();
|
||||
|
||||
@ -562,38 +564,38 @@ SchedGraph::addSSAEdge(SchedGraphNode* node,
|
||||
// if there is a node for it in the same graph, add an edge.
|
||||
SchedGraphNode* defNode = this->getGraphNodeForInstr(defMvec[i]);
|
||||
if (defNode != NULL && defNode != node)
|
||||
(void) new SchedGraphEdge(defNode, node, val);
|
||||
(void) new SchedGraphEdge(defNode, node, val);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
SchedGraph::addEdgesForInstruction(SchedGraphNode* node,
|
||||
NodeToRegRefMap& regToRefVecMap,
|
||||
SchedGraph::addEdgesForInstruction(const MachineInstr& minstr,
|
||||
RegToRefVecMap& regToRefVecMap,
|
||||
const TargetMachine& target)
|
||||
{
|
||||
const Instruction& instr = * node->getInstr(); // No dummy nodes here!
|
||||
const MachineInstr& minstr = * node->getMachineInstr();
|
||||
SchedGraphNode* node = this->getGraphNodeForInstr(&minstr);
|
||||
if (node == NULL)
|
||||
return;
|
||||
|
||||
// Add incoming edges for the following:
|
||||
// (1) operands of the machine instruction, including hidden operands
|
||||
// (2) machine register dependences
|
||||
// (3) other resource dependences for the machine instruction, if any
|
||||
// Also, note any uses or defs of machine registers.
|
||||
assert(node->getInstr() && "Should be no dummy nodes here!");
|
||||
const Instruction& instr = * node->getInstr();
|
||||
|
||||
// Add edges for all operands of the machine instruction.
|
||||
// Also, record all machine register references to add reg. deps. later.
|
||||
//
|
||||
for (unsigned i=0, numOps=minstr.getNumOperands(); i < numOps; i++)
|
||||
{
|
||||
const MachineOperand& mop = minstr.getOperand(i);
|
||||
|
||||
// if this writes to a machine register other than the hardwired
|
||||
// "zero" register used on many processors, record the reference.
|
||||
// "zero" register, record the reference.
|
||||
if (mop.getOperandType() == MachineOperand::MO_MachineRegister
|
||||
&& (mop.getMachineRegNum()
|
||||
== (unsigned) target.getRegInfo().getZeroRegNum()))
|
||||
!= (unsigned) target.getRegInfo().getZeroRegNum()))
|
||||
{
|
||||
regToRefVecMap[mop.getMachineRegNum()].
|
||||
push_back(make_pair(node, i));
|
||||
regToRefVecMap[mop.getMachineRegNum()].push_back(make_pair(node, i));
|
||||
}
|
||||
|
||||
// ignore all other def operands
|
||||
@ -621,10 +623,87 @@ SchedGraph::addEdgesForInstruction(SchedGraphNode* node,
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// add all true, anti,
|
||||
// and output dependences for this register. but ignore
|
||||
|
||||
// Add edges for values implicitly used by the machine instruction sequence
|
||||
// for the VM instruction but not made explicit operands. Examples include
|
||||
// function arguments to a Call instructions or the return value of a Ret
|
||||
// instruction. We'll conservatively add the dependences to every machine
|
||||
// machine instruction in the instruction sequence for this VM instr
|
||||
// (at least for now, there is never more than one machine instr).
|
||||
//
|
||||
const vector<const Value*>& implicitUses =
|
||||
instr.getMachineInstrVec().getImplicitUses();
|
||||
for (unsigned i=0; i < implicitUses.size(); ++i)
|
||||
addSSAEdge(node, implicitUses[i], target);
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
SchedGraph::addNonSSAEdgesForValue(const Instruction* instr,
|
||||
const TargetMachine& target)
|
||||
{
|
||||
assert(instr->isInstruction());
|
||||
if (instr->isPHINode())
|
||||
return;
|
||||
|
||||
MachineCodeForVMInstr& mvec = instr->getMachineInstrVec();
|
||||
const MachineInstrInfo& mii = target.getInstrInfo();
|
||||
RefVec refVec;
|
||||
|
||||
for (unsigned i=0, N=mvec.size(); i < N; i++)
|
||||
for (int o=0, N = mii.getNumOperands(mvec[i]->getOpCode()); o < N; o++)
|
||||
{
|
||||
const MachineOperand& op = mvec[i]->getOperand(o);
|
||||
|
||||
if ((op.getOperandType() == MachineOperand::MO_VirtualRegister ||
|
||||
op.getOperandType() == MachineOperand::MO_CCRegister)
|
||||
&& op.getVRegValue() == (Value*) instr)
|
||||
{
|
||||
// this operand is a definition or use of value `instr'
|
||||
SchedGraphNode* node = this->getGraphNodeForInstr(mvec[i]);
|
||||
assert(node && "No node for machine instruction in this BB?");
|
||||
refVec.push_back(make_pair(node, o));
|
||||
}
|
||||
}
|
||||
|
||||
// refVec is ordered by control flow order of the machine instructions
|
||||
for (unsigned i=0; i < refVec.size(); ++i)
|
||||
{
|
||||
SchedGraphNode* node = refVec[i].first;
|
||||
unsigned int opNum = refVec[i].second;
|
||||
bool isDef = node->getMachineInstr()->operandIsDefined(opNum);
|
||||
|
||||
if (isDef)
|
||||
// add output and/or anti deps to this definition
|
||||
for (unsigned p=0; p < i; ++p)
|
||||
{
|
||||
SchedGraphNode* prevNode = refVec[p].first;
|
||||
if (prevNode != node)
|
||||
{
|
||||
bool prevIsDef = prevNode->getMachineInstr()->
|
||||
operandIsDefined(refVec[p].second);
|
||||
new SchedGraphEdge(prevNode, node, SchedGraphEdge::DefUseDep,
|
||||
(prevIsDef)? SchedGraphEdge::OutputDep
|
||||
: SchedGraphEdge::AntiDep);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
SchedGraph::buildNodesforVMInstr(const TargetMachine& target,
|
||||
const Instruction* instr)
|
||||
{
|
||||
const MachineInstrInfo& mii = target.getInstrInfo();
|
||||
const MachineCodeForVMInstr& mvec = instr->getMachineInstrVec();
|
||||
for (unsigned i=0; i < mvec.size(); i++)
|
||||
if (! mii.isDummyPhiInstr(mvec[i]->getOpCode()))
|
||||
{
|
||||
SchedGraphNode* node = new SchedGraphNode(getNumNodes(),
|
||||
instr, mvec[i], target);
|
||||
this->noteGraphNodeForInstr(mvec[i], node);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -649,37 +728,46 @@ SchedGraph::buildGraph(const TargetMachine& target)
|
||||
// single basic block, hence the assertion. Each reference is identified
|
||||
// by the pair: <node, operand-number>.
|
||||
//
|
||||
NodeToRegRefMap regToRefVecMap;
|
||||
RegToRefVecMap regToRefVecMap;
|
||||
|
||||
// Make a dummy root node. We'll add edges to the real roots later.
|
||||
graphRoot = new SchedGraphNode(0, NULL, NULL, target);
|
||||
graphLeaf = new SchedGraphNode(1, NULL, NULL, target);
|
||||
|
||||
//----------------------------------------------------------------
|
||||
// First add nodes for all the machine instructions in the basic block.
|
||||
// This greatly simplifies identifing which edges to add.
|
||||
// First add nodes for all the machine instructions in the basic block
|
||||
// because this greatly simplifies identifying which edges to add.
|
||||
// Do this one VM instruction at a time since the SchedGraphNode needs that.
|
||||
// Also, remember the load/store instructions to add memory deps later.
|
||||
//----------------------------------------------------------------
|
||||
|
||||
for (BasicBlock::const_iterator II = bb->begin(); II != bb->end(); ++II)
|
||||
{
|
||||
const Instruction *instr = *II;
|
||||
const MachineCodeForVMInstr& mvec = instr->getMachineInstrVec();
|
||||
for (unsigned i=0, N=mvec.size(); i < N; i++)
|
||||
if (! mii.isDummyPhiInstr(mvec[i]->getOpCode()))
|
||||
{
|
||||
SchedGraphNode* node = new SchedGraphNode(getNumNodes(),
|
||||
instr, mvec[i], target);
|
||||
this->noteGraphNodeForInstr(mvec[i], node);
|
||||
}
|
||||
|
||||
// Build graph nodes for this VM instruction
|
||||
buildNodesforVMInstr(target, instr);
|
||||
|
||||
// Remember the load/store instructions to add memory deps later.
|
||||
if (instr->getOpcode() == Instruction::Load ||
|
||||
instr->getOpcode() == Instruction::Store)
|
||||
memVec.push_back(instr);
|
||||
}
|
||||
|
||||
//----------------------------------------------------------------
|
||||
// Now add the edges.
|
||||
// Now add edges for the following (all are incoming edges except (4)):
|
||||
// (1) operands of the machine instruction, including hidden operands
|
||||
// (2) machine register dependences
|
||||
// (3) memory load/store dependences
|
||||
// (3) other resource dependences for the machine instruction, if any
|
||||
// (4) output dependences when multiple machine instructions define the
|
||||
// same value; all must have been generated from a single VM instrn
|
||||
// (5) control dependences to branch instructions generated for the
|
||||
// terminator instruction of the BB. Because of delay slots and
|
||||
// 2-way conditional branches, multiple CD edges are needed
|
||||
// (see addCDEdges for details).
|
||||
// Also, note any uses or defs of machine registers.
|
||||
//
|
||||
//----------------------------------------------------------------
|
||||
|
||||
// First, add edges to the terminator instruction of the basic block.
|
||||
@ -689,10 +777,21 @@ SchedGraph::buildGraph(const TargetMachine& target)
|
||||
this->addMemEdges(memVec, target);
|
||||
|
||||
// Then add other edges for all instructions in the block.
|
||||
for (SchedGraph::iterator GI = this->begin(); GI != this->end(); ++GI)
|
||||
// Do this in machine code order and find all references to machine regs.
|
||||
MachineCodeForBasicBlock& mvec = bb->getMachineInstrVec();
|
||||
for (unsigned i=0, N=mvec.size(); i < N; i++)
|
||||
addEdgesForInstruction(*mvec[i], regToRefVecMap, target);
|
||||
|
||||
// Since the code is no longer in SSA form, add output dep. edges
|
||||
// between machine instructions that define the same Value, and anti-dep.
|
||||
// edges from those to other machine instructions for the same VM instr.
|
||||
// We assume that all machine instructions that define a value are
|
||||
// generated from the VM instruction corresponding to that value.
|
||||
//
|
||||
for (BasicBlock::const_iterator II = bb->begin(); II != bb->end(); ++II)
|
||||
{
|
||||
SchedGraphNode* node = (*GI).second;
|
||||
addEdgesForInstruction(node, regToRefVecMap, target);
|
||||
const Instruction *instr = *II;
|
||||
this->addNonSSAEdgesForValue(instr, target);
|
||||
}
|
||||
|
||||
// Then add edges for dependences on machine registers
|
||||
|
Loading…
Reference in New Issue
Block a user