6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-15 04:30:12 +00:00
Code Issues Projects Releases Wiki Activity

Use newly added API in MRegisterInfo.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16060 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Alkis Evlogimenos 2004-08-26 22:22:38 +00:00
parent bb4bdf4fe4
commit 5327801fb8
3 changed files with 8 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
include/llvm/CodeGen/LiveIntervalAnalysis.h
View File

@ -47,6 +47,8 @@ namespace llvm {
typedef std::map<unsigned, unsigned> Reg2RegMap; typedef std::map<unsigned, unsigned> Reg2RegMap;
Reg2RegMap r2rMap_; Reg2RegMap r2rMap_;
std::vector<bool> allocatableRegs_;
public: public:
struct InstrSlots struct InstrSlots
{ {

9
lib/CodeGen/LiveIntervalAnalysis.cpp
View File

@ -87,6 +87,7 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
tm_ = &fn.getTarget(); tm_ = &fn.getTarget();
mri_ = tm_->getRegisterInfo(); mri_ = tm_->getRegisterInfo();
lv_ = &getAnalysis<LiveVariables>(); lv_ = &getAnalysis<LiveVariables>();
allocatableRegs_ = mri_->getAllocatableSet(fn);
// number MachineInstrs // number MachineInstrs
unsigned miIndex = 0; unsigned miIndex = 0;
@ -484,7 +485,7 @@ void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
unsigned reg) { unsigned reg) {
if (MRegisterInfo::isVirtualRegister(reg)) if (MRegisterInfo::isVirtualRegister(reg))
handleVirtualRegisterDef(MBB, MI, getOrCreateInterval(reg)); handleVirtualRegisterDef(MBB, MI, getOrCreateInterval(reg));
else if (lv_->getAllocatablePhysicalRegisters()[reg]) { else if (allocatableRegs_[reg]) {
handlePhysicalRegisterDef(MBB, MI, getOrCreateInterval(reg)); handlePhysicalRegisterDef(MBB, MI, getOrCreateInterval(reg));
for (const unsigned* AS = mri_->getAliasSet(reg); *AS; ++AS) for (const unsigned* AS = mri_->getAliasSet(reg); *AS; ++AS)
handlePhysicalRegisterDef(MBB, MI, getOrCreateInterval(*AS)); handlePhysicalRegisterDef(MBB, MI, getOrCreateInterval(*AS));
@ -541,10 +542,8 @@ void LiveIntervals::joinIntervalsInMachineBB(MachineBasicBlock *MBB) {
// on not allocatable physical registers // on not allocatable physical registers
unsigned regA, regB; unsigned regA, regB;
if (TII.isMoveInstr(*mi, regA, regB) && if (TII.isMoveInstr(*mi, regA, regB) &&
(MRegisterInfo::isVirtualRegister(regA) || (MRegisterInfo::isVirtualRegister(regA) || allocatableRegs_[regA]) &&
lv_->getAllocatablePhysicalRegisters()[regA]) && (MRegisterInfo::isVirtualRegister(regB) || allocatableRegs_[regB])) {
(MRegisterInfo::isVirtualRegister(regB) ||
lv_->getAllocatablePhysicalRegisters()[regB])) {
// Get representative registers. // Get representative registers.
regA = rep(regA); regA = rep(regA);

2
lib/CodeGen/LiveIntervalAnalysis.h
View File

@ -47,6 +47,8 @@ namespace llvm {
typedef std::map<unsigned, unsigned> Reg2RegMap; typedef std::map<unsigned, unsigned> Reg2RegMap;
Reg2RegMap r2rMap_; Reg2RegMap r2rMap_;
std::vector<bool> allocatableRegs_;
public: public:
struct InstrSlots struct InstrSlots
{ {