6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-11-17 03:07:06 +00:00
Code Issues Projects Releases Wiki Activity

Rename BX/BRIND/etc patterns to clarify which is actually the BX instruction

Browse Source 
and which are pseudos.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120366 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2010-11-30 00:24:05 +00:00
parent 67077419c6
commit 532c2f1d50
2 changed files with 9 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
lib/Target/ARM/ARMCodeEmitter.cpp
View File

@ -779,10 +779,10 @@ void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
switch (Opcode) {
default:
llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
case ARM::BX:
case ARM::BMOVPCRX:
case ARM::BXr9:
case ARM::BMOVPCRXr9: {
case ARM::BX_CALL:
case ARM::BMOVPCRX_CALL:
case ARM::BXr9_CALL:
case ARM::BMOVPCRXr9_CALL: {
// First emit mov lr, pc
unsigned Binary = 0x01a0e00f;
Binary |= II->getPredicate(&MI) << ARMII::CondShift;

10
lib/Target/ARM/ARMInstrInfo.td
View File

@ -1221,7 +1221,7 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
// Indirect branches
let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
// ARMV4T and above
def BRIND : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
[(brind GPR:$dst)]>,
Requires<[IsARM, HasV4T]> {
bits<4> dst;
@ -1279,7 +1279,7 @@ let isCall = 1,
// ARMv4T
// Note: Restrict $func to the tGPR regclass to prevent it being in LR.
// FIXME: x2 insn patterns like this need to be pseudo instructions.
def BX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
def BX_CALL : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
IIC_Br, "mov\tlr, pc\n\tbx\t$func",
[(ARMcall_nolink tGPR:$func)]>,
Requires<[IsARM, HasV4T, IsNotDarwin]> {
@ -1289,7 +1289,7 @@ let isCall = 1,
}
// ARMv4
def BMOVPCRX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
def BMOVPCRX_CALL : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
[(ARMcall_nolink tGPR:$func)]>,
Requires<[IsARM, NoV4T, IsNotDarwin]> {
@ -1335,7 +1335,7 @@ let isCall = 1,
// ARMv4T
// Note: Restrict $func to the tGPR regclass to prevent it being in LR.
def BXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
def BXr9_CALL : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
IIC_Br, "mov\tlr, pc\n\tbx\t$func",
[(ARMcall_nolink tGPR:$func)]>,
Requires<[IsARM, HasV4T, IsDarwin]> {
@ -1345,7 +1345,7 @@ let isCall = 1,
}
// ARMv4
def BMOVPCRXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
def BMOVPCRXr9_CALL : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
[(ARMcall_nolink tGPR:$func)]>,
Requires<[IsARM, NoV4T, IsDarwin]> {