From 532dc2e1f2473b16b48566c1cbc9eefe94a4e58e Mon Sep 17 00:00:00 2001 From: Dan Gohman Date: Mon, 9 Jul 2007 20:59:04 +0000 Subject: [PATCH] Change getCopyToParts and getCopyFromParts to always use target-endian register ordering, for both physical and virtual registers. Update the PPC target lowering for calls to expect registers for the call result to already be in target order. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38471 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 48 +++++++------------ lib/Target/PowerPC/PPCISelLowering.cpp | 4 +- .../CodeGen/PowerPC/big-endian-call-result.ll | 13 +++++ 3 files changed, 33 insertions(+), 32 deletions(-) create mode 100644 test/CodeGen/PowerPC/big-endian-call-result.ll diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 3312542d390..373bce559d6 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -621,7 +621,6 @@ static SDOperand getCopyFromParts(SelectionDAG &DAG, unsigned NumParts, MVT::ValueType PartVT, MVT::ValueType ValueVT, - bool EndianOrder, ISD::NodeType AssertOp = ISD::DELETED_NODE) { if (!MVT::isVector(ValueVT) || NumParts == 1) { SDOperand Val = Parts[0]; @@ -631,7 +630,7 @@ static SDOperand getCopyFromParts(SelectionDAG &DAG, assert(NumParts == 2 && "Cannot expand to more than 2 elts yet!"); SDOperand Hi = Parts[1]; - if (EndianOrder && !DAG.getTargetLoweringInfo().isLittleEndian()) + if (!DAG.getTargetLoweringInfo().isLittleEndian()) std::swap(Val, Hi); return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi); } @@ -692,7 +691,7 @@ static SDOperand getCopyFromParts(SelectionDAG &DAG, // as appropriate. for (unsigned i = 0; i != NumParts; ++i) Ops[i] = getCopyFromParts(DAG, &Parts[i], 1, - PartVT, IntermediateVT, EndianOrder); + PartVT, IntermediateVT); } else if (NumParts > 0) { // If the intermediate type was expanded, build the intermediate operands // from the parts. @@ -701,7 +700,7 @@ static SDOperand getCopyFromParts(SelectionDAG &DAG, unsigned Factor = NumIntermediates / NumParts; for (unsigned i = 0; i != NumIntermediates; ++i) Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor, - PartVT, IntermediateVT, EndianOrder); + PartVT, IntermediateVT); } // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate @@ -718,8 +717,7 @@ static void getCopyToParts(SelectionDAG &DAG, SDOperand Val, SDOperand *Parts, unsigned NumParts, - MVT::ValueType PartVT, - bool EndianOrder) { + MVT::ValueType PartVT) { MVT::ValueType ValueVT = Val.getValueType(); if (!MVT::isVector(ValueVT) || NumParts == 1) { @@ -728,7 +726,7 @@ static void getCopyToParts(SelectionDAG &DAG, for (unsigned i = 0; i != NumParts; ++i) Parts[i] = DAG.getNode(ISD::EXTRACT_ELEMENT, PartVT, Val, DAG.getConstant(i, MVT::i32)); - if (EndianOrder && !DAG.getTargetLoweringInfo().isLittleEndian()) + if (!DAG.getTargetLoweringInfo().isLittleEndian()) std::reverse(Parts, Parts + NumParts); return; } @@ -789,7 +787,7 @@ static void getCopyToParts(SelectionDAG &DAG, // If the register was not expanded, promote or copy the value, // as appropriate. for (unsigned i = 0; i != NumParts; ++i) - getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT, EndianOrder); + getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT); } else if (NumParts > 0) { // If the intermediate type was expanded, split each the value into // legal parts. @@ -797,7 +795,7 @@ static void getCopyToParts(SelectionDAG &DAG, "Must expand into a divisible number of parts!"); unsigned Factor = NumParts / NumIntermediates; for (unsigned i = 0; i != NumIntermediates; ++i) - getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT, EndianOrder); + getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT); } } @@ -928,7 +926,7 @@ void SelectionDAGLowering::visitRet(ReturnInst &I) { unsigned NumParts = TLI.getNumRegisters(VT); MVT::ValueType PartVT = TLI.getRegisterType(VT); SmallVector Parts(NumParts); - getCopyToParts(DAG, RetOp, &Parts[0], NumParts, PartVT, true); + getCopyToParts(DAG, RetOp, &Parts[0], NumParts, PartVT); for (unsigned i = 0; i < NumParts; ++i) { NewValues.push_back(Parts[i]); NewValues.push_back(DAG.getConstant(false, MVT::i32)); @@ -2952,11 +2950,6 @@ void SelectionDAGLowering::visitCall(CallInst &I) { /// If the Flag pointer is NULL, no flag is used. SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG, SDOperand &Chain, SDOperand *Flag)const{ - // Get the list of registers, in the appropriate order. - std::vector R(Regs); - if (!DAG.getTargetLoweringInfo().isLittleEndian()) - std::reverse(R.begin(), R.end()); - // Copy the legal parts from the registers. unsigned NumParts = Regs.size(); SmallVector Parts(NumParts); @@ -2971,7 +2964,7 @@ SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG, } // Assemble the legal parts into the final value. - return getCopyFromParts(DAG, &Parts[0], NumParts, RegVT, ValueVT, false); + return getCopyFromParts(DAG, &Parts[0], NumParts, RegVT, ValueVT); } /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the @@ -2980,21 +2973,16 @@ SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG, /// If the Flag pointer is NULL, no flag is used. void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG, SDOperand &Chain, SDOperand *Flag) const { - // Get the list of registers, in the appropriate order. - std::vector R(Regs); - if (!DAG.getTargetLoweringInfo().isLittleEndian()) - std::reverse(R.begin(), R.end()); - // Get the list of the values's legal parts. unsigned NumParts = Regs.size(); SmallVector Parts(NumParts); - getCopyToParts(DAG, Val, &Parts[0], NumParts, RegVT, false); + getCopyToParts(DAG, Val, &Parts[0], NumParts, RegVT); // Copy the parts into the registers. for (unsigned i = 0; i != NumParts; ++i) { SDOperand Part = Flag ? - DAG.getCopyToReg(Chain, R[i], Parts[i], *Flag) : - DAG.getCopyToReg(Chain, R[i], Parts[i]); + DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag) : + DAG.getCopyToReg(Chain, Regs[i], Parts[i]); Chain = Part.getValue(0); if (Flag) *Flag = Part.getValue(1); @@ -3867,7 +3855,7 @@ TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { SmallVector Parts(NumParts); for (unsigned j = 0; j != NumParts; ++j) Parts[j] = SDOperand(Result, i++); - Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT, true)); + Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT)); break; } } @@ -3939,7 +3927,7 @@ TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, MVT::ValueType PartVT = getRegisterType(VT); unsigned NumParts = getNumRegisters(VT); SmallVector Parts(NumParts); - getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT, true); + getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT); for (unsigned i = 0; i != NumParts; ++i) { // if it isn't first piece, alignment must be 1 unsigned MyFlags = Flags; @@ -3979,7 +3967,7 @@ TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, SmallVector Results(NumRegs); for (unsigned i = 0; i != NumRegs; ++i) Results[i] = Res.getValue(i); - Res = getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT, false, AssertOp); + Res = getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT, AssertOp); } return std::make_pair(Res, Chain); @@ -4269,7 +4257,7 @@ SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, SmallVector Chains(NumRegs); // Copy the value by legal parts into sequential virtual registers. - getCopyToParts(DAG, Op, &Regs[0], NumRegs, RegisterVT, false); + getCopyToParts(DAG, Op, &Regs[0], NumRegs, RegisterVT); for (unsigned i = 0; i != NumRegs; ++i) Chains[i] = DAG.getCopyToReg(getRoot(), Reg + i, Regs[i]); return DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs); @@ -4406,8 +4394,8 @@ void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB, if (TI->getNumSuccessors()) SuccsHandled.resize(BB->getParent()->getNumBlockIDs()); - // Check successor nodes PHI nodes that expect a constant to be available from - // this block. + // Check successor nodes' PHI nodes that expect a constant to be available + // from this block. for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { BasicBlock *SuccBB = TI->getSuccessor(succ); if (!isa(SuccBB->begin())) continue; diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index a1fe4602d4d..e3e1e0c66c8 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -1774,9 +1774,9 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG, case MVT::Other: break; case MVT::i32: if (Op.Val->getValueType(1) == MVT::i32) { - Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32, InFlag).getValue(1); + Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1); ResultVals[0] = Chain.getValue(0); - Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, + Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32, Chain.getValue(2)).getValue(1); ResultVals[1] = Chain.getValue(0); NumResults = 2; diff --git a/test/CodeGen/PowerPC/big-endian-call-result.ll b/test/CodeGen/PowerPC/big-endian-call-result.ll new file mode 100644 index 00000000000..4885a623613 --- /dev/null +++ b/test/CodeGen/PowerPC/big-endian-call-result.ll @@ -0,0 +1,13 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \ +; RUN: grep {addic 4, 4, 1} +; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \ +; RUN: grep {addze 3, 3} + +declare i64 @foo(); + +define i64 @bar() +{ + %t = call i64 @foo() + %s = add i64 %t, 1 + ret i64 %s +}