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Eliminate a couple of fields from TargetRegisterClass: SubRegClasses and SuperRegClasses. These are not necessary. Also eliminate getSubRegisterRegClass and getSuperRegisterRegClass. These are slow and their results can change if register file names change. Just use TargetLowering::getRegClassFor() to get the right TargetRegisterClass instead.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62762 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-01-22 09:10:11 +00:00
parent e70909b8c9
commit 536ab130ec
7 changed files with 13 additions and 148 deletions
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5
include/llvm/CodeGen/FastISel.h
View File

@ -259,8 +259,9 @@ protected:
uint64_t Imm);
/// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
/// from a specified index of a superregister.
unsigned FastEmitInst_extractsubreg(unsigned Op0, uint32_t Idx);
/// from a specified index of a superregister to a specified type.
unsigned FastEmitInst_extractsubreg(MVT::SimpleValueType RetVT,
unsigned Op0, uint32_t Idx);
/// FastEmitBranch - Emit an unconditional branch to the given block,
/// unless it is the immediate (fall-through) successor, and update

29
include/llvm/Target/TargetRegisterInfo.h
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@ -60,8 +60,6 @@ private:
const vt_iterator VTs;
const sc_iterator SubClasses;
const sc_iterator SuperClasses;
const sc_iterator SubRegClasses;
const sc_iterator SuperRegClasses;
const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
const int CopyCost;
const iterator RegsBegin, RegsEnd;
@ -70,12 +68,9 @@ public:
const MVT *vts,
const TargetRegisterClass * const *subcs,
const TargetRegisterClass * const *supcs,
const TargetRegisterClass * const *subregcs,
const TargetRegisterClass * const *superregcs,
unsigned RS, unsigned Al, int CC,
iterator RB, iterator RE)
: ID(id), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
SubRegClasses(subregcs), SuperRegClasses(superregcs),
RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) {}
virtual ~TargetRegisterClass() {} // Allow subclasses
@ -170,30 +165,6 @@ public:
return I;
}
/// subregclasses_begin / subregclasses_end - Loop over all of
/// the subregister classes of this register class.
sc_iterator subregclasses_begin() const {
return SubRegClasses;
}
sc_iterator subregclasses_end() const {
sc_iterator I = SubRegClasses;
while (*I != NULL) ++I;
return I;
}
/// superregclasses_begin / superregclasses_end - Loop over all of
/// the superregister classes of this register class.
sc_iterator superregclasses_begin() const {
return SuperRegClasses;
}
sc_iterator superregclasses_end() const {
sc_iterator I = SuperRegClasses;
while (*I != NULL) ++I;
return I;
}
/// allocation_order_begin/end - These methods define a range of registers
/// which specify the registers in this class that are valid to register
/// allocate, and the preferred order to allocate them in. For example,

6
lib/CodeGen/SelectionDAG/FastISel.cpp
View File

@ -943,11 +943,11 @@ unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
return ResultReg;
}
unsigned FastISel::FastEmitInst_extractsubreg(unsigned Op0, uint32_t Idx) {
unsigned FastISel::FastEmitInst_extractsubreg(MVT::SimpleValueType RetVT,
unsigned Op0, uint32_t Idx) {
const TargetRegisterClass* RC = MRI.getRegClass(Op0);
const TargetRegisterClass* SRC = *(RC->subregclasses_begin()+Idx-1);
unsigned ResultReg = createResultReg(SRC);
unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG);
if (II.getNumDefs() >= 1)

35
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
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@ -333,33 +333,6 @@ void ScheduleDAGSDNodes::AddOperand(MachineInstr *MI, SDValue Op,
}
}
/// getSubRegisterRegClass - Returns the register class of specified register
/// class' "SubIdx"'th sub-register class.
static const TargetRegisterClass*
getSubRegisterRegClass(const TargetRegisterClass *TRC, unsigned SubIdx) {
// Pick the register class of the subregister
TargetRegisterInfo::regclass_iterator I =
TRC->subregclasses_begin() + SubIdx-1;
assert(I < TRC->subregclasses_end() &&
"Invalid subregister index for register class");
return *I;
}
/// getSuperRegisterRegClass - Returns the register class of a superreg A whose
/// "SubIdx"'th sub-register class is the specified register class and whose
/// type matches the specified type.
static const TargetRegisterClass*
getSuperRegisterRegClass(const TargetRegisterClass *TRC,
unsigned SubIdx, MVT VT) {
// Pick the register class of the superegister for this type
for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(),
E = TRC->superregclasses_end(); I != E; ++I)
if ((*I)->hasType(VT) && getSubRegisterRegClass(*I, SubIdx) == TRC)
return *I;
assert(false && "Couldn't find the register class");
return 0;
}
/// EmitSubregNode - Generate machine code for subreg nodes.
///
void ScheduleDAGSDNodes::EmitSubregNode(SDNode *Node,
@ -389,9 +362,7 @@ void ScheduleDAGSDNodes::EmitSubregNode(SDNode *Node,
MachineInstr *MI = BuildMI(MF, TII->get(TargetInstrInfo::EXTRACT_SUBREG));
// Figure out the register class to create for the destreg.
unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
const TargetRegisterClass *TRC = MRI.getRegClass(VReg);
const TargetRegisterClass *SRC = getSubRegisterRegClass(TRC, SubIdx);
const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getValueType(0));
if (VRBase) {
// Grab the destination register
@ -416,7 +387,6 @@ void ScheduleDAGSDNodes::EmitSubregNode(SDNode *Node,
SDValue N0 = Node->getOperand(0);
SDValue N1 = Node->getOperand(1);
SDValue N2 = Node->getOperand(2);
unsigned SubReg = getVR(N1, VRBaseMap);
unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
@ -425,8 +395,7 @@ void ScheduleDAGSDNodes::EmitSubregNode(SDNode *Node,
if (VRBase) {
TRC = MRI.getRegClass(VRBase);
} else {
TRC = getSuperRegisterRegClass(MRI.getRegClass(SubReg), SubIdx,
Node->getValueType(0));
TRC = TLI->getRegClassFor(Node->getValueType(0));
assert(TRC && "Couldn't determine register class for insert_subreg");
VRBase = MRI.createVirtualRegister(TRC); // Create the reg
}

3
lib/Target/X86/X86FastISel.cpp
View File

@ -1011,7 +1011,8 @@ bool X86FastISel::X86SelectTrunc(Instruction *I) {
BuildMI(MBB, TII.get(CopyOpc), CopyReg).addReg(InputReg);
// Then issue an extract_subreg.
unsigned ResultReg = FastEmitInst_extractsubreg(CopyReg, X86::SUBREG_8BIT);
unsigned ResultReg = FastEmitInst_extractsubreg(DstVT.getSimpleVT(),
CopyReg, X86::SUBREG_8BIT);
if (!ResultReg)
return false;

5
utils/TableGen/FastISelEmitter.cpp
View File

@ -440,7 +440,8 @@ void FastISelMap::PrintFunctionDefinitions(std::ostream &OS) {
Operands.PrintArguments(OS, *Memo.PhysRegs);
OS << ");\n";
} else {
OS << "extractsubreg(Op0, ";
OS << "extractsubreg(" << getName(RetVT);
OS << ", Op0, ";
OS << (unsigned)Memo.SubRegNo;
OS << ");\n";
}
@ -534,7 +535,7 @@ void FastISelMap::PrintFunctionDefinitions(std::ostream &OS) {
Operands.PrintArguments(OS, *Memo.PhysRegs);
OS << ");\n";
} else {
OS << "extractsubreg(Op0, ";
OS << "extractsubreg(RetVT, Op0, ";
OS << (unsigned)Memo.SubRegNo;
OS << ");\n";
}

78
utils/TableGen/RegisterInfoEmitter.cpp
View File

@ -240,83 +240,7 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
<< RegisterClasses[i].getName() << "RegClass;\n";
std::map<unsigned, std::set<unsigned> > SuperClassMap;
std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
OS << "\n";
// Emit the sub-register classes for each RegisterClass
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
const CodeGenRegisterClass &RC = RegisterClasses[rc];
// Give the register class a legal C name if it's anonymous.
std::string Name = RC.TheDef->getName();
OS << " // " << Name
<< " Sub-register Classes...\n"
<< " static const TargetRegisterClass* const "
<< Name << "SubRegClasses [] = {\n ";
bool Empty = true;
for (unsigned subrc = 0, subrcMax = RC.SubRegClasses.size();
subrc != subrcMax; ++subrc) {
unsigned rc2 = 0, e2 = RegisterClasses.size();
for (; rc2 != e2; ++rc2) {
const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
if (RC.SubRegClasses[subrc]->getName() == RC2.getName()) {
if (!Empty)
OS << ", ";
OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
Empty = false;
std::map<unsigned, std::set<unsigned> >::iterator SCMI =
SuperRegClassMap.find(rc2);
if (SCMI == SuperRegClassMap.end()) {
SuperRegClassMap.insert(std::make_pair(rc2, std::set<unsigned>()));
SCMI = SuperRegClassMap.find(rc2);
}
SCMI->second.insert(rc);
break;
}
}
if (rc2 == e2)
throw "Register Class member '" +
RC.SubRegClasses[subrc]->getName() +
"' is not a valid RegisterClass!";
}
OS << (!Empty ? ", " : "") << "NULL";
OS << "\n };\n\n";
}
// Emit the super-register classes for each RegisterClass
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
const CodeGenRegisterClass &RC = RegisterClasses[rc];
// Give the register class a legal C name if it's anonymous.
std::string Name = RC.TheDef->getName();
OS << " // " << Name
<< " Super-register Classes...\n"
<< " static const TargetRegisterClass* const "
<< Name << "SuperRegClasses [] = {\n ";
bool Empty = true;
std::map<unsigned, std::set<unsigned> >::iterator I =
SuperRegClassMap.find(rc);
if (I != SuperRegClassMap.end()) {
for (std::set<unsigned>::iterator II = I->second.begin(),
EE = I->second.end(); II != EE; ++II) {
const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
if (!Empty)
OS << ", ";
OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
Empty = false;
}
}
OS << (!Empty ? ", " : "") << "NULL";
OS << "\n };\n\n";
}
// Emit the sub-classes array for each RegisterClass
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
@ -398,8 +322,6 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
<< RC.getName() + "VTs" << ", "
<< RC.getName() + "Subclasses" << ", "
<< RC.getName() + "Superclasses" << ", "
<< RC.getName() + "SubRegClasses" << ", "
<< RC.getName() + "SuperRegClasses" << ", "
<< RC.SpillSize/8 << ", "
<< RC.SpillAlignment/8 << ", "
<< RC.CopyCost << ", "