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Added InstrSchedClass to each of the PowerPC Instructions.

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Note that when adding new instructions that you should refer to the table at the
bottom of PPCSchedule.td.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23830 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Laskey
2005-10-19 19:51:16 +00:00
parent 3d92544261
commit 538421411a
9 changed files with 427 additions and 389 deletions
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13
lib/Target/Target.td
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@@ -112,6 +112,12 @@ class RegisterClass<string namespace, ValueType regType, int alignment,
}
//===----------------------------------------------------------------------===//
// Pull in the common support for scheduling
//
include "../TargetSchedule.td"
//===----------------------------------------------------------------------===//
// Instruction set description - These classes correspond to the C++ classes in
// the Target/TargetInstrInfo.h file.
@@ -147,6 +153,8 @@ class Instruction {
bit isTerminator = 0; // Is this part of the terminator for a basic block?
bit hasDelaySlot = 0; // Does this instruction have an delay slot?
bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
InstrItinClass Itinerary; // Execution steps used for scheduling.
}
@@ -241,11 +249,6 @@ class Target {
list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
}
//===----------------------------------------------------------------------===//
// Pull in the common support for scheduling
//
include "../TargetSchedule.td"
//===----------------------------------------------------------------------===//
// SubtargetFeature - A characteristic of the chip set.
//