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NEON VST4(multiple 4 element structures) assembly parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148764 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
8abe7e3364
commit
539aab771f
@ -6264,6 +6264,66 @@ def VLD4qWB_register_Asm_32 :
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(ins VecListFourQ:$list, addrmode6:$addr,
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(ins VecListFourQ:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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rGPR:$Rm, pred:$p)>;
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// VST4 multiple structure pseudo-instructions. These need special handling for
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// the vector operands that the normal instructions don't yet model.
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// FIXME: Remove these when the register classes and instructions are updated.
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def VST4dAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
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(ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
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def VST4dAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
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(ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
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def VST4dAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
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(ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
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def VST4qAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
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(ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
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def VST4qAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
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(ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
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def VST4qAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
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(ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
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def VST4dWB_fixed_Asm_8 :
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NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",
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(ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
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def VST4dWB_fixed_Asm_16 :
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NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
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(ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
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def VST4dWB_fixed_Asm_32 :
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NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
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(ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
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def VST4qWB_fixed_Asm_8 :
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NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",
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(ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
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def VST4qWB_fixed_Asm_16 :
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NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
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(ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
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def VST4qWB_fixed_Asm_32 :
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NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
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(ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
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def VST4dWB_register_Asm_8 :
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NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",
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(ins VecListFourD:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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def VST4dWB_register_Asm_16 :
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NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
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(ins VecListFourD:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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def VST4dWB_register_Asm_32 :
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NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
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(ins VecListFourD:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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def VST4qWB_register_Asm_8 :
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NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",
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(ins VecListFourQ:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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def VST4qWB_register_Asm_16 :
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NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
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(ins VecListFourQ:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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def VST4qWB_register_Asm_32 :
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NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
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(ins VecListFourQ:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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// VMOV takes an optional datatype suffix
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// VMOV takes an optional datatype suffix
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defm : VFPDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
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defm : VFPDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
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(VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
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(VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
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@ -5247,6 +5247,26 @@ static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
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case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8;
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case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8;
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case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
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case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
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case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
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case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
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// VST4
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case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
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case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
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case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
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case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
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case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
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case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
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case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
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case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
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case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
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case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
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case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
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case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
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case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8;
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case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
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case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
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case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8;
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case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
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case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
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}
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}
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}
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}
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@ -6016,6 +6036,83 @@ processInstruction(MCInst &Inst,
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return true;
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return true;
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}
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}
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// VST4 multiple 3-element structure instructions.
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case ARM::VST4dAsm_8:
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case ARM::VST4dAsm_16:
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case ARM::VST4dAsm_32:
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case ARM::VST4qAsm_8:
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case ARM::VST4qAsm_16:
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case ARM::VST4qAsm_32: {
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MCInst TmpInst;
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unsigned Spacing;
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TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
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TmpInst.addOperand(Inst.getOperand(1)); // Rn
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TmpInst.addOperand(Inst.getOperand(2)); // alignment
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TmpInst.addOperand(Inst.getOperand(0)); // Vd
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing * 2));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing * 3));
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TmpInst.addOperand(Inst.getOperand(3)); // CondCode
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TmpInst.addOperand(Inst.getOperand(4));
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Inst = TmpInst;
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return true;
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}
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case ARM::VST4dWB_fixed_Asm_8:
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case ARM::VST4dWB_fixed_Asm_16:
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case ARM::VST4dWB_fixed_Asm_32:
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case ARM::VST4qWB_fixed_Asm_8:
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case ARM::VST4qWB_fixed_Asm_16:
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case ARM::VST4qWB_fixed_Asm_32: {
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MCInst TmpInst;
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unsigned Spacing;
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TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
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TmpInst.addOperand(Inst.getOperand(1)); // Rn
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TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
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TmpInst.addOperand(Inst.getOperand(2)); // alignment
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TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
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TmpInst.addOperand(Inst.getOperand(0)); // Vd
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing * 2));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing * 3));
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TmpInst.addOperand(Inst.getOperand(3)); // CondCode
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TmpInst.addOperand(Inst.getOperand(4));
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Inst = TmpInst;
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return true;
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}
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case ARM::VST4dWB_register_Asm_8:
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case ARM::VST4dWB_register_Asm_16:
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case ARM::VST4dWB_register_Asm_32:
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case ARM::VST4qWB_register_Asm_8:
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case ARM::VST4qWB_register_Asm_16:
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case ARM::VST4qWB_register_Asm_32: {
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MCInst TmpInst;
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unsigned Spacing;
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TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
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TmpInst.addOperand(Inst.getOperand(1)); // Rn
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TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
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TmpInst.addOperand(Inst.getOperand(2)); // alignment
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TmpInst.addOperand(Inst.getOperand(3)); // Rm
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TmpInst.addOperand(Inst.getOperand(0)); // Vd
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing * 2));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing * 3));
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TmpInst.addOperand(Inst.getOperand(4)); // CondCode
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TmpInst.addOperand(Inst.getOperand(5));
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Inst = TmpInst;
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return true;
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}
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// Handle the Thumb2 mode MOV complex aliases.
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// Handle the Thumb2 mode MOV complex aliases.
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case ARM::t2MOVsr:
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case ARM::t2MOVsr:
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case ARM::t2MOVSsr: {
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case ARM::t2MOVSsr: {
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@ -99,23 +99,45 @@
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@ CHECK: vst3.32 {d5, d7, d9}, [r4]! @ encoding: [0x8d,0x55,0x04,0xf4]
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@ CHECK: vst3.32 {d5, d7, d9}, [r4]! @ encoding: [0x8d,0x55,0x04,0xf4]
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@ vst4.8 {d16, d17, d18, d19}, [r0, :64]
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vst4.8 {d16, d17, d18, d19}, [r1, :64]
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@ vst4.16 {d16, d17, d18, d19}, [r0, :128]
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vst4.16 {d16, d17, d18, d19}, [r2, :128]
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@ vst4.8 {d16, d18, d20, d22}, [r0, :256]!
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vst4.32 {d16, d17, d18, d19}, [r3, :256]
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@ vst4.8 {d17, d19, d21, d23}, [r0, :256]!
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vst4.8 {d17, d19, d21, d23}, [r5, :256]
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@ vst4.16 {d16, d18, d20, d22}, [r0]!
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vst4.16 {d17, d19, d21, d23}, [r7]
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@ vst4.16 {d17, d19, d21, d23}, [r0]!
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vst4.32 {d16, d18, d20, d22}, [r8]
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@ vst4.32 {d16, d18, d20, d22}, [r0]!
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@ vst4.32 {d17, d19, d21, d23}, [r0]!
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@ FIXME: vst4.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x00,0x40,0xf4]
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vst4.s8 {d16, d17, d18, d19}, [r1, :64]!
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@ FIXME: vst4.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x00,0x40,0xf4]
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vst4.s16 {d16, d17, d18, d19}, [r2, :128]!
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@ FIXME: vst4.8 {d16, d18, d20, d22}, [r0, :256]! @ encoding: [0x3d,0x01,0x40,0xf4]
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vst4.s32 {d16, d17, d18, d19}, [r3, :256]!
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@ FIXME: vst4.8 {d17, d19, d21, d23}, [r0, :256]! @ encoding: [0x3d,0x11,0x40,0xf4]
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vst4.u8 {d17, d19, d21, d23}, [r5, :256]!
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@ FIXME: vst4.16 {d16, d18, d20, d22}, [r0]! @ encoding: [0x4d,0x01,0x40,0xf4]
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vst4.u16 {d17, d19, d21, d23}, [r7]!
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@ FIXME: vst4.16 {d17, d19, d21, d23}, [r0]! @ encoding: [0x4d,0x11,0x40,0xf4]
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vst4.u32 {d16, d18, d20, d22}, [r8]!
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@ FIXME: vst4.32 {d16, d18, d20, d22}, [r0]! @ encoding: [0x8d,0x01,0x40,0xf4]
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@ FIXME: vst4.32 {d17, d19, d21, d23}, [r0]! @ encoding: [0x8d,0x11,0x40,0xf4]
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vst4.p8 {d16, d17, d18, d19}, [r1, :64], r8
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vst4.p16 {d16, d17, d18, d19}, [r2], r7
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vst4.f32 {d16, d17, d18, d19}, [r3, :64], r5
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vst4.i8 {d16, d18, d20, d22}, [r4, :256], r2
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vst4.i16 {d16, d18, d20, d22}, [r6], r3
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vst4.i32 {d17, d19, d21, d23}, [r9], r4
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@ CHECK: vst4.8 {d16, d17, d18, d19}, [r1, :64] @ encoding: [0x1f,0x00,0x41,0xf4]
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@ CHECK: vst4.16 {d16, d17, d18, d19}, [r2, :128] @ encoding: [0x6f,0x00,0x42,0xf4]
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@ CHECK: vst4.32 {d16, d17, d18, d19}, [r3, :256] @ encoding: [0xbf,0x00,0x43,0xf4]
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@ CHECK: vst4.8 {d17, d19, d21, d23}, [r5, :256] @ encoding: [0x3f,0x11,0x45,0xf4]
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@ CHECK: vst4.16 {d17, d19, d21, d23}, [r7] @ encoding: [0x4f,0x11,0x47,0xf4]
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@ CHECK: vst4.32 {d16, d18, d20, d22}, [r8] @ encoding: [0x8f,0x01,0x48,0xf4]
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@ CHECK: vst4.8 {d16, d17, d18, d19}, [r1, :64]! @ encoding: [0x1d,0x00,0x41,0xf4]
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@ CHECK: vst4.16 {d16, d17, d18, d19}, [r2, :128]! @ encoding: [0x6d,0x00,0x42,0xf4]
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@ CHECK: vst4.32 {d16, d17, d18, d19}, [r3, :256]! @ encoding: [0xbd,0x00,0x43,0xf4]
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@ CHECK: vst4.8 {d17, d19, d21, d23}, [r5, :256]! @ encoding: [0x3d,0x11,0x45,0xf4]
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@ CHECK: vst4.16 {d17, d19, d21, d23}, [r7]! @ encoding: [0x4d,0x11,0x47,0xf4]
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@ CHECK: vst4.32 {d16, d18, d20, d22}, [r8]! @ encoding: [0x8d,0x01,0x48,0xf4]
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@ CHECK: vst4.8 {d16, d17, d18, d19}, [r1, :64], r8 @ encoding: [0x18,0x00,0x41,0xf4]
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@ CHECK: vst4.16 {d16, d17, d18, d19}, [r2], r7 @ encoding: [0x47,0x00,0x42,0xf4]
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@ CHECK: vst4.32 {d16, d17, d18, d19}, [r3, :64], r5 @ encoding: [0x95,0x00,0x43,0xf4]
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@ CHECK: vst4.8 {d16, d18, d20, d22}, [r4, :256], r2 @ encoding: [0x32,0x01,0x44,0xf4]
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@ CHECK: vst4.16 {d16, d18, d20, d22}, [r6], r3 @ encoding: [0x43,0x01,0x46,0xf4]
|
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@ CHECK: vst4.32 {d17, d19, d21, d23}, [r9], r4 @ encoding: [0x84,0x11,0x49,0xf4]
|
||||||
|
|
||||||
|
|
||||||
vst2.8 {d16[1], d17[1]}, [r0, :16]
|
vst2.8 {d16[1], d17[1]}, [r0, :16]
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user