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Use TableGen'erated pseudo lowering for ARM.

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Hook up the TableGen lowering for simple pseudo instructions for ARM and
use it for a subset of the many pseudos the backend has as proof of concept.

More conversions to come.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134705 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2011-07-08 17:40:42 +00:00
parent 86f9adb8be
commit 53e3fc463e
8 changed files with 196 additions and 216 deletions
Download Patch File Download Diff File Expand all files Collapse all files

94
lib/Target/ARM/ARMAsmPrinter.cpp
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@@ -1069,48 +1069,18 @@ void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
extern cl::opt<bool> EnableARMEHABI;
// Simple pseudo-instructions have their lowering (with expansion to real
// instructions) auto-generated.
#include "ARMGenMCPseudoLowering.inc"
void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
// Do any auto-generated pseudo lowerings.
if (emitPseudoExpansionLowering(OutStreamer, MI))
return;
// Check for manual lowerings.
unsigned Opc = MI->getOpcode();
switch (Opc) {
default: break;
case ARM::B: {
// B is just a Bcc with an 'always' predicate.
MCInst TmpInst;
LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
TmpInst.setOpcode(ARM::Bcc);
// Add predicate operands.
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
TmpInst.addOperand(MCOperand::CreateReg(0));
OutStreamer.EmitInstruction(TmpInst);
return;
}
case ARM::LDMIA_RET: {
// LDMIA_RET is just a normal LDMIA_UPD instruction that targets PC and as
// such has additional code-gen properties and scheduling information.
// To emit it, we just construct as normal and set the opcode to LDMIA_UPD.
MCInst TmpInst;
LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
TmpInst.setOpcode(ARM::LDMIA_UPD);
OutStreamer.EmitInstruction(TmpInst);
return;
}
case ARM::t2LDMIA_RET: {
// As above for LDMIA_RET. Map to the tPOP instruction.
MCInst TmpInst;
LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
TmpInst.setOpcode(ARM::t2LDMIA_UPD);
OutStreamer.EmitInstruction(TmpInst);
return;
}
case ARM::tPOP_RET: {
// As above for LDMIA_RET. Map to the tPOP instruction.
MCInst TmpInst;
LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
TmpInst.setOpcode(ARM::tPOP);
OutStreamer.EmitInstruction(TmpInst);
return;
}
case ARM::t2MOVi32imm: assert(0 && "Should be lowered by thumb2it pass");
case ARM::DBG_VALUE: {
if (isVerbose() && OutStreamer.hasRawTextSupport()) {
@@ -1121,14 +1091,6 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
}
return;
}
case ARM::tBfar: {
MCInst TmpInst;
TmpInst.setOpcode(ARM::tBL);
TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::Create(
MI->getOperand(0).getMBB()->getSymbol(), OutContext)));
OutStreamer.EmitInstruction(TmpInst);
return;
}
case ARM::LEApcrel:
case ARM::tLEApcrel:
case ARM::t2LEApcrel: {
@@ -1159,19 +1121,6 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
OutStreamer.EmitInstruction(TmpInst);
return;
}
case ARM::MOVPCRX: {
MCInst TmpInst;
TmpInst.setOpcode(ARM::MOVr);
TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
// Add predicate operands.
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
TmpInst.addOperand(MCOperand::CreateReg(0));
// Add 's' bit operand (always reg0 for this)
TmpInst.addOperand(MCOperand::CreateReg(0));
OutStreamer.EmitInstruction(TmpInst);
return;
}
// Darwin call instructions are just normal call instructions with different
// clobber semantics (they clobber R9).
case ARM::BLr9:
@@ -1912,31 +1861,6 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
OutStreamer.EmitInstruction(TmpInst);
return;
}
// These are the pseudos created to comply with stricter operand restrictions
// on ARMv5. Lower them now to "normal" instructions, since all the
// restrictions are already satisfied.
case ARM::MULv5:
EmitPatchedInstruction(MI, ARM::MUL);
return;
case ARM::MLAv5:
EmitPatchedInstruction(MI, ARM::MLA);
return;
case ARM::SMULLv5:
EmitPatchedInstruction(MI, ARM::SMULL);
return;
case ARM::UMULLv5:
EmitPatchedInstruction(MI, ARM::UMULL);
return;
case ARM::SMLALv5:
EmitPatchedInstruction(MI, ARM::SMLAL);
return;
case ARM::UMLALv5:
EmitPatchedInstruction(MI, ARM::UMLAL);
return;
case ARM::UMAALv5:
EmitPatchedInstruction(MI, ARM::UMAAL);
return;
}
MCInst TmpInst;