6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-19 19:29:31 +00:00
Code Issues Projects Releases Wiki Activity

add patterns for FP stores

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24790 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-12-17 20:47:16 +00:00
parent d55e1ca5ef
commit 53ec2035eb
2 changed files with 24 additions and 40 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
lib/Target/Sparc/SparcInstrInfo.td
View File

@ -206,29 +206,21 @@ def STDri : F3_2<3, 0b000111,
// Section B.5 - Store Floating-point Instructions, p. 97
def STFrr : F3_1<3, 0b100100,
(ops MEMrr:$addr, IntRegs:$src),
"st $src, [$addr]", []>;
(ops MEMrr:$addr, FPRegs:$src),
"st $src, [$addr]",
[(store FPRegs:$src, ADDRrr:$addr)]>;
def STFri : F3_2<3, 0b100100,
(ops MEMri:$addr, IntRegs:$src),
"st $src, [$addr]", []>;
(ops MEMri:$addr, FPRegs:$src),
"st $src, [$addr]",
[(store FPRegs:$src, ADDRri:$addr)]>;
def STDFrr : F3_1<3, 0b100111,
(ops MEMrr:$addr, IntRegs:$src),
"std $src, [$addr]", []>;
(ops MEMrr:$addr, DFPRegs:$src),
"std $src, [$addr]",
[(store DFPRegs:$src, ADDRrr:$addr)]>;
def STDFri : F3_2<3, 0b100111,
(ops MEMri:$addr, IntRegs:$src),
"std $src, [$addr]", []>;
def STFSRrr : F3_1<3, 0b100101,
(ops MEMrr:$addr, IntRegs:$src),
"st $src, [$addr]", []>;
def STFSRri : F3_2<3, 0b100101,
(ops MEMri:$addr, IntRegs:$src),
"st $src, [$addr]", []>;
def STDFQrr : F3_1<3, 0b100110,
(ops MEMrr:$addr, IntRegs:$src),
"std $src, [$addr]", []>;
def STDFQri : F3_2<3, 0b100110,
(ops MEMri:$addr, IntRegs:$src),
"std $src, [$addr]", []>;
(ops MEMri:$addr, DFPRegs:$src),
"std $src, [$addr]",
[(store DFPRegs:$src, ADDRri:$addr)]>;
// Section B.9 - SETHI Instruction, p. 104
def SETHIi: F2_1<0b100,

32
lib/Target/SparcV8/SparcV8InstrInfo.td
View File

@ -206,29 +206,21 @@ def STDri : F3_2<3, 0b000111,
// Section B.5 - Store Floating-point Instructions, p. 97
def STFrr : F3_1<3, 0b100100,
(ops MEMrr:$addr, IntRegs:$src),
"st $src, [$addr]", []>;
(ops MEMrr:$addr, FPRegs:$src),
"st $src, [$addr]",
[(store FPRegs:$src, ADDRrr:$addr)]>;
def STFri : F3_2<3, 0b100100,
(ops MEMri:$addr, IntRegs:$src),
"st $src, [$addr]", []>;
(ops MEMri:$addr, FPRegs:$src),
"st $src, [$addr]",
[(store FPRegs:$src, ADDRri:$addr)]>;
def STDFrr : F3_1<3, 0b100111,
(ops MEMrr:$addr, IntRegs:$src),
"std $src, [$addr]", []>;
(ops MEMrr:$addr, DFPRegs:$src),
"std $src, [$addr]",
[(store DFPRegs:$src, ADDRrr:$addr)]>;
def STDFri : F3_2<3, 0b100111,
(ops MEMri:$addr, IntRegs:$src),
"std $src, [$addr]", []>;
def STFSRrr : F3_1<3, 0b100101,
(ops MEMrr:$addr, IntRegs:$src),
"st $src, [$addr]", []>;
def STFSRri : F3_2<3, 0b100101,
(ops MEMri:$addr, IntRegs:$src),
"st $src, [$addr]", []>;
def STDFQrr : F3_1<3, 0b100110,
(ops MEMrr:$addr, IntRegs:$src),
"std $src, [$addr]", []>;
def STDFQri : F3_2<3, 0b100110,
(ops MEMri:$addr, IntRegs:$src),
"std $src, [$addr]", []>;
(ops MEMri:$addr, DFPRegs:$src),
"std $src, [$addr]",
[(store DFPRegs:$src, ADDRri:$addr)]>;
// Section B.9 - SETHI Instruction, p. 104
def SETHIi: F2_1<0b100,