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Code clean up. No functionality changes.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77301 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-07-28 06:24:12 +00:00
parent 6495f63945
commit 542383d93b
1 changed files with 32 additions and 21 deletions
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53
lib/Target/ARM/ARMBaseRegisterInfo.cpp
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@ -439,6 +439,7 @@ bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const {
MFI->isFrameAddressTaken());
}
/// estimateStackSize - Estimate and return the size of the frame.
static unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) {
const MachineFrameInfo *FFI = MF.getFrameInfo();
int Offset = 0;
@ -457,6 +458,36 @@ static unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) {
return (unsigned)Offset;
}
/// estimateRSStackSizeLimit - Look at each instruction that references stack
/// frames and return the stack size limit beyond which some of these
/// instructions will require scratch register during their expansion later.
static unsigned estimateRSStackSizeLimit(MachineFunction &MF,
const ARMBaseInstrInfo &TII) {
unsigned Limit = (1 << 12) - 1;
for (MachineFunction::iterator BB = MF.begin(),E = MF.end();BB != E; ++BB) {
for (MachineBasicBlock::iterator I= BB->begin(); I != BB->end(); ++I) {
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
if (I->getOperand(i).isFI()) {
unsigned Opcode = I->getOpcode();
const TargetInstrDesc &Desc = TII.get(Opcode);
unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
if (AddrMode == ARMII::AddrMode3 ||
AddrMode == ARMII::AddrModeT2_i8) {
return (1 << 8) - 1;
} else if (AddrMode == ARMII::AddrMode5 ||
AddrMode == ARMII::AddrModeT2_i8s4) {
unsigned ThisLimit = ((1 << 8) - 1) * 4;
if (ThisLimit < Limit)
Limit = ThisLimit;
}
break; // At most one FI per instruction
}
}
}
return Limit;
}
void
ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
RegScavenger *RS) const {
@ -609,27 +640,7 @@ ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
// register scavenging.
if (RS && !ExtraCSSpill && !AFI->isThumb1OnlyFunction()) {
MachineFrameInfo *MFI = MF.getFrameInfo();
unsigned Size = estimateStackSize(MF, MFI);
unsigned Limit = (1 << 12) - 1;
for (MachineFunction::iterator BB = MF.begin(),E = MF.end();BB != E; ++BB)
for (MachineBasicBlock::iterator I= BB->begin(); I != BB->end(); ++I) {
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
if (I->getOperand(i).isFI()) {
unsigned Opcode = I->getOpcode();
const TargetInstrDesc &Desc = TII.get(Opcode);
unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
if (AddrMode == ARMII::AddrMode3) {
Limit = (1 << 8) - 1;
goto DoneEstimating;
} else if (AddrMode == ARMII::AddrMode5) {
unsigned ThisLimit = ((1 << 8) - 1) * 4;
if (ThisLimit < Limit)
Limit = ThisLimit;
}
}
}
DoneEstimating:
if (Size >= Limit) {
if (estimateStackSize(MF, MFI) >= estimateRSStackSizeLimit(MF, TII)) {
// If any non-reserved CS register isn't spilled, just spill one or two
// extra. That should take care of it!
unsigned NumExtras = TargetAlign / 4;