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[PPC64LE] Correct vperm -> shuffle transform for little endian
As discussed in cfe commit r210279, the correct little-endian semantics for the vec_perm Altivec interfaces are implemented by reversing the order of the input vectors and complementing the permute control vector. This converts the desired permute from little endian element order into the big endian element order that the underlying PowerPC vperm instruction uses. This is represented with a ppc_altivec_vperm intrinsic function. The instruction combining pass contains code to convert a ppc_altivec_vperm intrinsic into a vector shuffle operation when the intrinsic has a permute control vector (mask) that is a constant. However, the vector shuffle operation assumes that vector elements are in natural order for their endianness, so for little endian code we will get the wrong result with the existing transformation. This patch reverses the semantic change to vec_perm that was performed in altivec.h by once again swapping the input operands and complementing the permute control vector, returning the element ordering to little endian. The correctness of this code is tested by the new perm.c test added in a previous patch, and by other tests in the test suite that fail without this patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210282 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -800,6 +800,11 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
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case Intrinsic::ppc_altivec_vperm:
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case Intrinsic::ppc_altivec_vperm:
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// Turn vperm(V1,V2,mask) -> shuffle(V1,V2,mask) if mask is a constant.
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// Turn vperm(V1,V2,mask) -> shuffle(V1,V2,mask) if mask is a constant.
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// Note that ppc_altivec_vperm has a big-endian bias, so when creating
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// a vectorshuffle for little endian, we must undo the transformation
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// performed on vec_perm in altivec.h. That is, we must complement
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// the permutation mask with respect to 31 and reverse the order of
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// V1 and V2.
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if (Constant *Mask = dyn_cast<Constant>(II->getArgOperand(2))) {
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if (Constant *Mask = dyn_cast<Constant>(II->getArgOperand(2))) {
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assert(Mask->getType()->getVectorNumElements() == 16 &&
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assert(Mask->getType()->getVectorNumElements() == 16 &&
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"Bad type for intrinsic!");
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"Bad type for intrinsic!");
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@ -832,10 +837,14 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
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unsigned Idx =
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unsigned Idx =
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cast<ConstantInt>(Mask->getAggregateElement(i))->getZExtValue();
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cast<ConstantInt>(Mask->getAggregateElement(i))->getZExtValue();
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Idx &= 31; // Match the hardware behavior.
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Idx &= 31; // Match the hardware behavior.
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if (DL && DL->isLittleEndian())
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Idx = 31 - Idx;
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if (!ExtractedElts[Idx]) {
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if (!ExtractedElts[Idx]) {
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Value *Op0ToUse = (DL && DL->isLittleEndian()) ? Op1 : Op0;
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Value *Op1ToUse = (DL && DL->isLittleEndian()) ? Op0 : Op1;
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ExtractedElts[Idx] =
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ExtractedElts[Idx] =
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Builder->CreateExtractElement(Idx < 16 ? Op0 : Op1,
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Builder->CreateExtractElement(Idx < 16 ? Op0ToUse : Op1ToUse,
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Builder->getInt32(Idx&15));
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Builder->getInt32(Idx&15));
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}
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}
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