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Some basic store support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112752 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -106,6 +106,7 @@ class ARMFastISel : public FastISel {
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// Instruction selection routines.
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virtual bool ARMSelectLoad(const Instruction *I);
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virtual bool ARMSelectStore(const Instruction *I);
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// Utility routines.
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private:
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@ -113,6 +114,7 @@ class ARMFastISel : public FastISel {
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bool isLoadTypeLegal(const Type *Ty, EVT &VT);
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bool ARMEmitLoad(EVT VT, unsigned &ResultReg, unsigned Reg, int Offset);
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bool ARMLoadAlloca(const Instruction *I);
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bool ARMStoreAlloca(const Instruction *I);
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bool ARMComputeRegOffset(const Value *Obj, unsigned &Reg, int &Offset);
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bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
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@ -444,6 +446,43 @@ bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg,
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return true;
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}
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bool ARMFastISel::ARMStoreAlloca(const Instruction *I) {
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Value *Op1 = I->getOperand(1);
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// Verify it's an alloca.
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if (const AllocaInst *AI = dyn_cast<AllocaInst>(Op1)) {
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DenseMap<const AllocaInst*, int>::iterator SI =
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FuncInfo.StaticAllocaMap.find(AI);
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if (SI != FuncInfo.StaticAllocaMap.end()) {
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TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy());
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unsigned Reg = getRegForValue(I->getOperand(0));
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// Make sure we can get this into a register.
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if (Reg == 0) return false;
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TII.storeRegToStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
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Reg, true /*isKill*/, SI->second, RC,
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TM.getRegisterInfo());
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return true;
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}
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}
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return false;
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}
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bool ARMFastISel::ARMSelectStore(const Instruction *I) {
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// If we're an alloca we know we have a frame index and can emit the store
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// quickly.
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if (ARMStoreAlloca(I))
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return true;
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// Yay type legalization
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EVT VT;
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if (!isLoadTypeLegal(I->getType(), VT))
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return false;
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return false;
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}
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bool ARMFastISel::ARMSelectLoad(const Instruction *I) {
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// If we're an alloca we know we have a frame index and can emit the load
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// directly in short order.
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@ -496,6 +535,8 @@ bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
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switch (I->getOpcode()) {
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case Instruction::Load:
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return ARMSelectLoad(I);
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case Instruction::Store:
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return ARMSelectStore(I);
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default: break;
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}
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return false;
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