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[fast-isel] Fold "urem x, pow2" -> "and x, pow2-1". This should fix the 271%
execution-time regression for nsieve-bits on the ARMv7 -O0 -g nightly tester. This may also improve compile-time on architectures that would otherwise generate a libcall for urem (e.g., ARM) or fall back to the DAG selector. rdar://10810716 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153230 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -395,6 +395,13 @@ bool FastISel::SelectBinaryOp(const User *I, unsigned ISDOpcode) {
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ISDOpcode = ISD::SRA;
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}
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// Transform "urem x, pow2" -> "and x, pow2-1".
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if (ISDOpcode == ISD::UREM && isa<BinaryOperator>(I) &&
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isPowerOf2_64(Imm)) {
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--Imm;
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ISDOpcode = ISD::AND;
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}
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unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
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Op0IsKill, Imm, VT.getSimpleVT());
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if (ResultReg == 0) return false;
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@ -217,3 +217,12 @@ entry:
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; THUMB: vcmpe.f32 s0, #0
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ret i1 %4
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}
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; ARM: @urem_fold
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; THUMB: @urem_fold
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; ARM: and r0, r0, #31
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; THUMB: and r0, r0, #31
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define i32 @urem_fold(i32 %a) nounwind {
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%rem = urem i32 %a, 32
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ret i32 %rem
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}
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