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TableGen subtarget emitter. Format and emit data tables for the new machine model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164060 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -20,6 +20,7 @@
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#include "llvm/TableGen/Record.h"
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#include "llvm/TableGen/TableGenBackend.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/Format.h"
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#include <algorithm>
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#include <map>
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#include <string>
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@ -83,6 +84,7 @@ class SubtargetEmitter {
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Record *FindReadAdvance(Record *ReadDef, const CodeGenProcModel &ProcModel);
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void GenSchedClassTables(const CodeGenProcModel &ProcModel,
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SchedClassTables &SchedTables);
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void EmitSchedClassTables(SchedClassTables &SchedTables, raw_ostream &OS);
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void EmitProcessorModels(raw_ostream &OS);
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void EmitProcessorLookup(raw_ostream &OS);
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void EmitSchedModel(raw_ostream &OS);
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@ -901,6 +903,103 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
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}
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}
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// Emit SchedClass tables for all processors and associated global tables.
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void SubtargetEmitter::EmitSchedClassTables(SchedClassTables &SchedTables,
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raw_ostream &OS) {
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// Emit global WriteProcResTable.
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OS << "\n// {ProcResourceIdx, Cycles}\n"
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<< "extern const llvm::MCWriteProcResEntry "
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<< Target << "WriteProcResTable[] = {\n"
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<< " { 0, 0}, // Invalid\n";
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for (unsigned WPRIdx = 1, WPREnd = SchedTables.WriteProcResources.size();
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WPRIdx != WPREnd; ++WPRIdx) {
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MCWriteProcResEntry &WPREntry = SchedTables.WriteProcResources[WPRIdx];
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OS << " {" << format("%2d", WPREntry.ProcResourceIdx) << ", "
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<< format("%2d", WPREntry.Cycles) << "}";
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if (WPRIdx + 1 < WPREnd)
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OS << ',';
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OS << " // #" << WPRIdx << '\n';
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}
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OS << "}; // " << Target << "WriteProcResTable\n";
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// Emit global WriteLatencyTable.
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OS << "\n// {Cycles, WriteResourceID}\n"
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<< "extern const llvm::MCWriteLatencyEntry "
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<< Target << "WriteLatencyTable[] = {\n"
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<< " { 0, 0}, // Invalid\n";
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for (unsigned WLIdx = 1, WLEnd = SchedTables.WriteLatencies.size();
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WLIdx != WLEnd; ++WLIdx) {
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MCWriteLatencyEntry &WLEntry = SchedTables.WriteLatencies[WLIdx];
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OS << " {" << format("%2d", WLEntry.Cycles) << ", "
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<< format("%2d", WLEntry.WriteResourceID) << "}";
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if (WLIdx + 1 < WLEnd)
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OS << ',';
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OS << " // #" << WLIdx << " "
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<< SchedModels.getSchedWrite(WLEntry.WriteResourceID).Name << '\n';
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}
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OS << "}; // " << Target << "WriteLatencyTable\n";
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// Emit global ReadAdvanceTable.
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OS << "\n// {UseIdx, WriteResourceID, Cycles}\n"
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<< "extern const llvm::MCReadAdvanceEntry "
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<< Target << "ReadAdvanceTable[] = {\n"
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<< " {0, 0, 0}, // Invalid\n";
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for (unsigned RAIdx = 1, RAEnd = SchedTables.ReadAdvanceEntries.size();
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RAIdx != RAEnd; ++RAIdx) {
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MCReadAdvanceEntry &RAEntry = SchedTables.ReadAdvanceEntries[RAIdx];
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OS << " {" << RAEntry.UseIdx << ", "
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<< format("%2d", RAEntry.WriteResourceID) << ", "
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<< format("%2d", RAEntry.Cycles) << "}";
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if (RAIdx + 1 < RAEnd)
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OS << ',';
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OS << " // #" << RAIdx << '\n';
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}
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OS << "}; // " << Target << "ReadAdvanceTable\n";
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// Emit a SchedClass table for each processor.
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for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
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PE = SchedModels.procModelEnd(); PI != PE; ++PI) {
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if (!PI->hasInstrSchedModel())
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continue;
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std::vector<MCSchedClassDesc> &SCTab =
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SchedTables.ProcSchedClasses[1 + PI - SchedModels.procModelBegin()];
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OS << "\n// {Name, NumMicroOps, BeginGroup, EndGroup,"
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<< " WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}\n";
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OS << "static const llvm::MCSchedClassDesc "
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<< PI->ModelName << "SchedClasses[] = {\n";
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// The first class is always invalid. We no way to distinguish it except by
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// name and position.
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assert(SchedModels.getSchedClass(0).Name == "NoItinerary"
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&& "invalid class not first");
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OS << " {DBGFIELD(\"InvalidSchedClass\") "
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<< MCSchedClassDesc::InvalidNumMicroOps
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<< ", 0, 0, 0, 0, 0, 0, 0, 0},\n";
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for (unsigned SCIdx = 1, SCEnd = SCTab.size(); SCIdx != SCEnd; ++SCIdx) {
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MCSchedClassDesc &MCDesc = SCTab[SCIdx];
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const CodeGenSchedClass &SchedClass = SchedModels.getSchedClass(SCIdx);
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OS << " {DBGFIELD(\"" << SchedClass.Name << "\") ";
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if (SchedClass.Name.size() < 18)
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OS.indent(18 - SchedClass.Name.size());
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OS << MCDesc.NumMicroOps
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<< ", " << MCDesc.BeginGroup << ", " << MCDesc.EndGroup
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<< ", " << format("%2d", MCDesc.WriteProcResIdx)
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<< ", " << MCDesc.NumWriteProcResEntries
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<< ", " << format("%2d", MCDesc.WriteLatencyIdx)
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<< ", " << MCDesc.NumWriteLatencyEntries
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<< ", " << format("%2d", MCDesc.ReadAdvanceIdx)
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<< ", " << MCDesc.NumReadAdvanceEntries << "}";
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if (SCIdx + 1 < SCEnd)
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OS << ',';
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OS << " // #" << SCIdx << '\n';
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}
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OS << "}; // " << PI->ModelName << "SchedClasses\n";
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}
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}
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void SubtargetEmitter::EmitProcessorModels(raw_ostream &OS) {
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// For each processor model.
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for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
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@ -983,17 +1082,20 @@ void SubtargetEmitter::EmitSchedModel(raw_ostream &OS) {
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EmitStageAndOperandCycleData(OS, ProcItinLists);
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EmitItineraries(OS, ProcItinLists);
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}
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// Emit the processor machine model
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EmitProcessorModels(OS);
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// Emit the processor lookup data
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EmitProcessorLookup(OS);
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OS << "\n// ===============================================================\n"
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<< "// Data tables for the new per-operand machine model.\n";
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SchedClassTables SchedTables;
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for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
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PE = SchedModels.procModelEnd(); PI != PE; ++PI) {
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GenSchedClassTables(*PI, SchedTables);
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}
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EmitSchedClassTables(SchedTables, OS);
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// Emit the processor machine model
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EmitProcessorModels(OS);
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// Emit the processor lookup data
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EmitProcessorLookup(OS);
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OS << "#undef DBGFIELD";
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}
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@ -1089,6 +1191,7 @@ void SubtargetEmitter::run(raw_ostream &OS) {
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OS << Target << "SubTypeKV, ";
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else
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OS << "0, ";
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OS << '\n'; OS.indent(22);
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if (SchedModels.hasItineraryClasses()) {
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OS << Target << "ProcSchedKV, "
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<< Target << "Stages, "
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@ -1135,8 +1238,15 @@ void SubtargetEmitter::run(raw_ostream &OS) {
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OS << "namespace llvm {\n";
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OS << "extern const llvm::SubtargetFeatureKV " << Target << "FeatureKV[];\n";
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OS << "extern const llvm::SubtargetFeatureKV " << Target << "SubTypeKV[];\n";
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OS << "extern const llvm::SubtargetInfoKV " << Target << "ProcSchedKV[];\n";
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OS << "extern const llvm::MCWriteProcResEntry "
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<< Target << "WriteProcResTable[];\n";
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OS << "extern const llvm::MCWriteLatencyEntry "
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<< Target << "WriteLatencyTable[];\n";
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OS << "extern const llvm::MCReadAdvanceEntry "
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<< Target << "ReadAdvanceTable[];\n";
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if (SchedModels.hasItineraryClasses()) {
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OS << "extern const llvm::SubtargetInfoKV " << Target << "ProcSchedKV[];\n";
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OS << "extern const llvm::InstrStage " << Target << "Stages[];\n";
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OS << "extern const unsigned " << Target << "OperandCycles[];\n";
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OS << "extern const unsigned " << Target << "ForwardingPaths[];\n";
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@ -1162,6 +1272,7 @@ void SubtargetEmitter::run(raw_ostream &OS) {
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} else
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OS << "0, 0, 0, 0, ";
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OS << NumFeatures << ", " << NumProcs << ");\n}\n\n";
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OS << "} // End llvm namespace \n";
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OS << "#endif // GET_SUBTARGETINFO_CTOR\n\n";
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