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AArch64: stop claiming that NEON registers are usable for now.

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If vector types have legal register classes, then LLVM bypasses LegalizeTypes
on them, which causes faults currently since the code to handle them isn't in
place.

This fixes test failures when AArch64 is the default target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175172 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover 2013-02-14 16:22:14 +00:00
parent 5bd6cb2dab
commit 5464c301c4
1 changed files with 0 additions and 11 deletions
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11
lib/Target/AArch64/AArch64ISelLowering.cpp
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@ -57,17 +57,6 @@ AArch64TargetLowering::AArch64TargetLowering(AArch64TargetMachine &TM)
addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
// And the vectors
addRegisterClass(MVT::v8i8, &AArch64::VPR64RegClass);
addRegisterClass(MVT::v4i16, &AArch64::VPR64RegClass);
addRegisterClass(MVT::v2i32, &AArch64::VPR64RegClass);
addRegisterClass(MVT::v2f32, &AArch64::VPR64RegClass);
addRegisterClass(MVT::v16i8, &AArch64::VPR128RegClass);
addRegisterClass(MVT::v8i16, &AArch64::VPR128RegClass);
addRegisterClass(MVT::v4i32, &AArch64::VPR128RegClass);
addRegisterClass(MVT::v4f32, &AArch64::VPR128RegClass);
addRegisterClass(MVT::v2f64, &AArch64::VPR128RegClass);
computeRegisterProperties();
// Some atomic operations can be folded into load-acquire or store-release