diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h
index 1e14a11d594..fbc933d5d5d 100644
--- a/include/llvm/Target/TargetLowering.h
+++ b/include/llvm/Target/TargetLowering.h
@@ -119,7 +119,7 @@ public:
 
   /// getSetCCResultType - Return the ValueType of the result of setcc
   /// operations.
-  virtual MVT getSetCCResultType(const SDValue &) const;
+  virtual MVT getSetCCResultType(MVT VT) const;
 
   /// getBooleanContents - For targets without i1 registers, this gives the
   /// nature of the high-bits of boolean values held in types wider than i1.
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index bc3117cf0c9..4fb50e30dbe 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -2799,7 +2799,8 @@ SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
     return N2;
   
   // Determine if the condition we're dealing with is constant
-  SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false);
+  SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
+                              N0, N1, CC, false);
   if (SCC.getNode()) AddToWorkList(SCC.getNode());
 
   if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
@@ -4242,7 +4243,7 @@ SDValue DAGCombiner::visitBR_CC(SDNode *N) {
   SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
   
   // Use SimplifySetCC to simplify SETCC's.
-  SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS),
+  SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()),
                                CondLHS, CondRHS, CC->get(), false);
   if (Simp.getNode()) AddToWorkList(Simp.getNode());
 
@@ -5437,7 +5438,8 @@ SDValue DAGCombiner::SimplifySelectCC(SDValue N0, SDValue N1,
   ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
 
   // Determine if the condition we're dealing with is constant
-  SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false);
+  SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
+                              N0, N1, CC, false);
   if (SCC.getNode()) AddToWorkList(SCC.getNode());
   ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
 
@@ -5517,7 +5519,8 @@ SDValue DAGCombiner::SimplifySelectCC(SDValue N0, SDValue N1,
     SDValue Temp, SCC;
     // cast from setcc result type to select result type
     if (LegalTypes) {
-      SCC  = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC);
+      SCC  = DAG.getSetCC(TLI.getSetCCResultType(N0.getValueType()),
+                          N0, N1, CC);
       if (N2.getValueType().bitsLT(SCC.getValueType()))
         Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
       else
@@ -5543,8 +5546,8 @@ SDValue DAGCombiner::SimplifySelectCC(SDValue N0, SDValue N1,
   if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
     MVT XType = N0.getValueType();
     if (!LegalOperations ||
-        TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(N0))) {
-      SDValue Res = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC);
+        TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) {
+      SDValue Res = DAG.getSetCC(TLI.getSetCCResultType(XType), N0, N1, CC);
       if (Res.getValueType() != VT)
         Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
       return Res;
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 2c0d9ddcc1c..97b526f4fef 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -2092,7 +2092,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     Tmp3 = Node->getOperand(3);              // RHS
     Tmp4 = Node->getOperand(1);              // CC
 
-    LegalizeSetCC(TLI.getSetCCResultType(Tmp2), Tmp2, Tmp3, Tmp4);
+    LegalizeSetCC(TLI.getSetCCResultType(Tmp2.getValueType()), Tmp2, Tmp3,Tmp4);
     LastCALLSEQ_END = DAG.getEntryNode();
 
     // If we didn't get both a LHS and RHS back from LegalizeSetCC,
@@ -2994,7 +2994,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     Tmp4 = LegalizeOp(Node->getOperand(3));   // False
     SDValue CC = Node->getOperand(4);
     
-    LegalizeSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2, CC);
+    LegalizeSetCC(TLI.getSetCCResultType(Tmp1.getValueType()), Tmp1, Tmp2, CC);
     
     // If we didn't get both a LHS and RHS back from LegalizeSetCC,
     // the LHS is a legal SETCC itself.  In this case, we need to compare
@@ -3109,7 +3109,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
       for (unsigned i = 0; i < NumElems; ++i) {
         SDValue In1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, TmpEltVT,
                                   Tmp1, DAG.getIntPtrConstant(i));
-        Ops[i] = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(In1), In1,
+        Ops[i] = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(TmpEltVT), In1,
                              DAG.getNode(ISD::EXTRACT_VECTOR_ELT, TmpEltVT,
                                          Tmp2, DAG.getIntPtrConstant(i)),
                              CC);
@@ -3371,7 +3371,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
         MVT IVT =
           Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
         SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
-        SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit),
+        SignBit = DAG.getSetCC(TLI.getSetCCResultType(IVT),
                                SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
         // Get the absolute value of the result.
         SDValue AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
@@ -3736,7 +3736,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
         break;
       case ISD::CTTZ:
         //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
-        Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
+        Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1.getValueType()), Tmp1,
                             DAG.getConstant(NVT.getSizeInBits(), NVT),
                             ISD::SETEQ);
         Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
@@ -3798,8 +3798,8 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
         // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
         MVT VT = Node->getValueType(0);
         Tmp2 = DAG.getConstantFP(0.0, VT);
-        Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
-                            ISD::SETUGT);
+        Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1.getValueType()),
+                            Tmp1, Tmp2, ISD::SETUGT);
         Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
         Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
         break;
@@ -4069,8 +4069,8 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
           APInt x = APInt::getSignBit(NVT.getSizeInBits());
           (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
           Tmp2 = DAG.getConstantFP(apf, VT);
-          Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)),
-                            Node->getOperand(0), Tmp2, ISD::SETLT);
+          Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(VT), Node->getOperand(0),
+                              Tmp2, ISD::SETLT);
           True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
           False = DAG.getNode(ISD::FP_TO_SINT, NVT,
                               DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
@@ -4484,15 +4484,15 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
     assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
     break;
 
-  case ISD::SETCC:
-    assert(isTypeLegal(TLI.getSetCCResultType(Node->getOperand(0)))
+  case ISD::SETCC: {
+    MVT VT0 = Node->getOperand(0).getValueType();
+    assert(isTypeLegal(TLI.getSetCCResultType(VT0))
            && "SetCC type is not legal??");
-    Result = DAG.getNode(ISD::SETCC,
-                         TLI.getSetCCResultType(Node->getOperand(0)),
+    Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(VT0),
                          Node->getOperand(0), Node->getOperand(1),
                          Node->getOperand(2));
     break;
-    
+  }
   case ISD::TRUNCATE:
     switch (getTypeAction(Node->getOperand(0).getValueType())) {
     case Legal:
@@ -4898,7 +4898,7 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
       break;
     case ISD::CTTZ:
       // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
-      Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
+      Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1.getValueType()), Tmp1,
                           DAG.getConstant(NVT.getSizeInBits(), NVT),
                           ISD::SETEQ);
       Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
@@ -5167,12 +5167,14 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
       Tmp2 = DAG.getConstant(0, MVT::i32);
       CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
       if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
-        Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
-                           CC);
+        Tmp1 = DAG.getNode(ISD::SETCC,
+                           TLI.getSetCCResultType(Tmp1.getValueType()),
+                           Tmp1, Tmp2, CC);
         LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2).getNode(),
                             false /*sign irrelevant*/, Dummy);
-        Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2,
-                           DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
+        Tmp2 = DAG.getNode(ISD::SETCC,
+                           TLI.getSetCCResultType(LHS.getValueType()), LHS,
+                           Tmp2, DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
         Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
         Tmp2 = SDValue();
       }
@@ -5192,13 +5194,15 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
       //         BNE crN, L:
       //         FCMPU crN, lo1, lo2
       // The following can be improved, but not that much.
-      Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 
-                                                         ISD::SETOEQ);
-      Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode);
+      Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
+                          LHSHi, RHSHi, ISD::SETOEQ);
+      Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
+                          LHSLo, RHSLo, CCCode);
       Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
-      Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 
-                                                         ISD::SETUNE);
-      Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode);
+      Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
+                          LHSHi, RHSHi, ISD::SETUNE);
+      Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
+                          LHSHi, RHSHi, CCCode);
       Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
       Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
       Tmp2 = SDValue();
@@ -5256,15 +5260,17 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
       // NOTE: on targets without efficient SELECT of bools, we can always use
       // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
       TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
-      Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo,
-                               LowCC, false, DagCombineInfo);
+      Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
+                               LHSLo, RHSLo, LowCC, false, DagCombineInfo);
       if (!Tmp1.getNode())
-        Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
-      Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
-                               CCCode, false, DagCombineInfo);
+        Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
+                            LHSLo, RHSLo, LowCC);
+      Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
+                               LHSHi, RHSHi, CCCode, false, DagCombineInfo);
       if (!Tmp2.getNode())
-        Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi,
-                           RHSHi,CC);
+        Tmp2 = DAG.getNode(ISD::SETCC,
+                           TLI.getSetCCResultType(LHSHi.getValueType()),
+                           LHSHi, RHSHi,CC);
       
       ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
       ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
@@ -5281,11 +5287,12 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
         Tmp1 = Tmp2;
         Tmp2 = SDValue();
       } else {
-        Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
-                                   ISD::SETEQ, false, DagCombineInfo);
+        Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
+                                   LHSHi, RHSHi, ISD::SETEQ, false,
+                                   DagCombineInfo);
         if (!Result.getNode())
-          Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
-                              ISD::SETEQ);
+          Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
+                              LHSHi, RHSHi, ISD::SETEQ);
         Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
                                         Result, Tmp1, Tmp2));
         Tmp1 = Result;
@@ -5909,9 +5916,9 @@ ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source) {
     // signed, then adjust the result if the sign bit is set.
     SDValue SignedConv = ExpandIntToFP(true, DestTy, Source);
 
-    SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
-                                     DAG.getConstant(0, Hi.getValueType()),
-                                     ISD::SETLT);
+    SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi.getValueType()),
+                                   Hi, DAG.getConstant(0, Hi.getValueType()),
+                                   ISD::SETLT);
     SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
     SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
                                       SignSet, Four, Zero);
@@ -6050,9 +6057,9 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
   assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
   SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
 
-  SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0,
-                                   DAG.getConstant(0, Op0.getValueType()),
-                                   ISD::SETLT);
+  SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0.getValueType()),
+                                 Op0, DAG.getConstant(0, Op0.getValueType()),
+                                 ISD::SETLT);
   SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
   SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
                                     SignSet, Four, Zero);
@@ -6458,8 +6465,8 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
     ExpandOp(Node->getOperand(0), Lo, Hi);
     SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
     SDValue HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
-    SDValue TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC,
-                                        ISD::SETNE);
+    SDValue TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(NVT), HLZ, BitsC,
+                                      ISD::SETNE);
     SDValue LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
     LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
 
@@ -6473,8 +6480,8 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
     ExpandOp(Node->getOperand(0), Lo, Hi);
     SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
     SDValue LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
-    SDValue BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC,
-                                        ISD::SETNE);
+    SDValue BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(NVT), LTZ, BitsC,
+                                      ISD::SETNE);
     SDValue HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
     HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
 
@@ -6950,12 +6957,12 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
       if (Node->getOpcode() == ISD::ADD) {
         Lo = DAG.getNode(ISD::ADD, NVT, LoOps, 2);
         Hi = DAG.getNode(ISD::ADD, NVT, HiOps, 2);
-        SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(Lo),
+        SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(NVT),
                                     Lo, LoOps[0], ISD::SETULT);
         SDValue Carry1 = DAG.getNode(ISD::SELECT, NVT, Cmp1,
                                      DAG.getConstant(1, NVT), 
                                      DAG.getConstant(0, NVT));
-        SDValue Cmp2 = DAG.getSetCC(TLI.getSetCCResultType(Lo),
+        SDValue Cmp2 = DAG.getSetCC(TLI.getSetCCResultType(NVT),
                                     Lo, LoOps[1], ISD::SETULT);
         SDValue Carry2 = DAG.getNode(ISD::SELECT, NVT, Cmp2,
                                     DAG.getConstant(1, NVT), 
@@ -7875,8 +7882,8 @@ SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
   case ISD::VSETCC: {
     SDValue Op0 = ScalarizeVectorOp(Op.getOperand(0));
     SDValue Op1 = ScalarizeVectorOp(Op.getOperand(1));
-    Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0), Op0, Op1,
-                         Op.getOperand(2));
+    Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0.getValueType()),
+                         Op0, Op1, Op.getOperand(2));
     Result = DAG.getNode(ISD::SELECT, NewVT, Result,
                          DAG.getConstant(-1ULL, NewVT),
                          DAG.getConstant(0ULL, NewVT));
diff --git a/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
index 9a766e283a3..3cfaa27335f 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
@@ -594,10 +594,10 @@ void DAGTypeLegalizer::SoftenSetCCOperands(SDValue &NewLHS, SDValue &NewRHS,
   NewRHS = DAG.getConstant(0, RetVT);
   CCCode = TLI.getCmpLibcallCC(LC1);
   if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
-    SDValue Tmp = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(NewLHS),
+    SDValue Tmp = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(RetVT),
                                 NewLHS, NewRHS, DAG.getCondCode(CCCode));
     NewLHS = MakeLibCall(LC2, RetVT, Ops, 2, false/*sign irrelevant*/);
-    NewLHS = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(NewLHS), NewLHS,
+    NewLHS = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(RetVT), NewLHS,
                          NewRHS, DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
     NewLHS = DAG.getNode(ISD::OR, Tmp.getValueType(), Tmp, NewLHS);
     NewRHS = SDValue();
@@ -1216,11 +1216,15 @@ void DAGTypeLegalizer::FloatExpandSetCCOperands(SDValue &NewLHS,
   //         FCMPU crN, lo1, lo2
   // The following can be improved, but not that much.
   SDValue Tmp1, Tmp2, Tmp3;
-  Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETOEQ);
-  Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode);
+  Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
+                      LHSHi, RHSHi, ISD::SETOEQ);
+  Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
+                      LHSLo, RHSLo, CCCode);
   Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
-  Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETUNE);
-  Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode);
+  Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
+                      LHSHi, RHSHi, ISD::SETUNE);
+  Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
+                      LHSHi, RHSHi, CCCode);
   Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
   NewLHS = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
   NewRHS = SDValue();   // LHS is the result, not a compare.
diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 7ae53eb7a9d..caa92b51ef7 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -464,7 +464,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
 }
 
 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
-  MVT SVT = TLI.getSetCCResultType(N->getOperand(0));
+  MVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType());
   assert(isTypeLegal(SVT) && "Illegal SetCC type!");
 
   // Get the SETCC result using the canonical SETCC type.
@@ -728,25 +728,42 @@ SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
   assert(OpNo == 1 && "only know how to promote condition");
   SDValue Cond = GetPromotedInteger(N->getOperand(1));  // Promote condition.
 
-  // Make sure the extra bits coming from type promotion conform to
-  // getBooleanContents.
+  // Promote all the way up to SVT, the canonical SetCC type.
+  MVT SVT = TLI.getSetCCResultType(MVT::Other);
+  assert(isTypeLegal(SVT) && "Illegal SetCC type!");
+  assert(Cond.getValueType().bitsLE(SVT) && "Unexpected SetCC type!");
+
+  // Make sure the extra bits conform to getBooleanContents.  There are
+  // two sets of extra bits: those in Cond, which come from type promotion,
+  // and those we need to add to have the final type be SVT (for most targets
+  // this last set of bits is empty).
   unsigned CondBits = Cond.getValueSizeInBits();
+  ISD::NodeType ExtendCode;
   switch (TLI.getBooleanContents()) {
   default:
     assert(false && "Unknown BooleanContent!");
   case TargetLowering::UndefinedBooleanContent:
-    // The promoted value, which may contain rubbish in the upper bits, is fine.
+    // Extend to SVT by adding rubbish.
+    ExtendCode = ISD::ANY_EXTEND;
     break;
   case TargetLowering::ZeroOrOneBooleanContent:
+    ExtendCode = ISD::ZERO_EXTEND;
     if (!DAG.MaskedValueIsZero(Cond,APInt::getHighBitsSet(CondBits,CondBits-1)))
-      Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
+      // All extra bits need to be cleared.  Do this by zero extending the
+      // original condition value all the way to SVT.
+      Cond = N->getOperand(1);
     break;
-  case TargetLowering::ZeroOrNegativeOneBooleanContent:
-    if (DAG.ComputeNumSignBits(Cond) != CondBits)
-      Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, Cond.getValueType(), Cond,
-                         DAG.getValueType(MVT::i1));
+  case TargetLowering::ZeroOrNegativeOneBooleanContent: {
+    ExtendCode = ISD::SIGN_EXTEND;
+    unsigned SignBits = DAG.ComputeNumSignBits(Cond);
+    if (SignBits != CondBits)
+      // All extra bits need to be sign extended.  Do this by sign extending the
+      // original condition value all the way to SVT.
+      Cond = N->getOperand(1);
     break;
   }
+  }
+  Cond = DAG.getNode(ExtendCode, SVT, Cond);
 
   // The chain (Op#0) and basic block destination (Op#2) are always legal types.
   return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Cond,
@@ -851,13 +868,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
   SDValue Cond = GetPromotedInteger(N->getOperand(0));
 
   // Promote all the way up to SVT, the canonical SetCC type.
-  // FIXME: Not clear what value to pass to getSetCCResultType.
-  // [This only matters for CellSPU since all other targets
-  // ignore the argument.]  We used to pass Cond, resulting in
-  // SVT = MVT::i8, but CellSPU has no select patterns for i8,
-  // causing an abort later.  Passing the result type works
-  // around the problem.
-  MVT SVT = TLI.getSetCCResultType(N->getOperand(1));
+  MVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType());
   assert(isTypeLegal(SVT) && "Illegal SetCC type!");
   assert(Cond.getValueType().bitsLE(SVT) && "Unexpected SetCC type!");
 
@@ -1244,12 +1255,12 @@ void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
     if (N->getOpcode() == ISD::ADD) {
       Lo = DAG.getNode(ISD::ADD, NVT, LoOps, 2);
       Hi = DAG.getNode(ISD::ADD, NVT, HiOps, 2);
-      SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo, LoOps[0],
+      SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(NVT), Lo, LoOps[0],
                                   ISD::SETULT);
       SDValue Carry1 = DAG.getNode(ISD::SELECT, NVT, Cmp1,
                                    DAG.getConstant(1, NVT),
                                    DAG.getConstant(0, NVT));
-      SDValue Cmp2 = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo, LoOps[1],
+      SDValue Cmp2 = DAG.getSetCC(TLI.getSetCCResultType(NVT), Lo, LoOps[1],
                                   ISD::SETULT);
       SDValue Carry2 = DAG.getNode(ISD::SELECT, NVT, Cmp2,
                                    DAG.getConstant(1, NVT), Carry1);
@@ -1257,8 +1268,9 @@ void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
     } else {
       Lo = DAG.getNode(ISD::SUB, NVT, LoOps, 2);
       Hi = DAG.getNode(ISD::SUB, NVT, HiOps, 2);
-      SDValue Cmp = DAG.getSetCC(TLI.getSetCCResultType(LoOps[0]),
-                                 LoOps[0], LoOps[1], ISD::SETULT);
+      SDValue Cmp =
+        DAG.getSetCC(TLI.getSetCCResultType(LoOps[0].getValueType()),
+                     LoOps[0], LoOps[1], ISD::SETULT);
       SDValue Borrow = DAG.getNode(ISD::SELECT, NVT, Cmp,
                                    DAG.getConstant(1, NVT),
                                    DAG.getConstant(0, NVT));
@@ -1391,7 +1403,7 @@ void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
   GetExpandedInteger(N->getOperand(0), Lo, Hi);
   MVT NVT = Lo.getValueType();
 
-  SDValue HiNotZero = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
+  SDValue HiNotZero = DAG.getSetCC(TLI.getSetCCResultType(NVT), Hi,
                                    DAG.getConstant(0, NVT), ISD::SETNE);
 
   SDValue LoLZ = DAG.getNode(ISD::CTLZ, NVT, Lo);
@@ -1419,7 +1431,7 @@ void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
   GetExpandedInteger(N->getOperand(0), Lo, Hi);
   MVT NVT = Lo.getValueType();
 
-  SDValue LoNotZero = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo,
+  SDValue LoNotZero = DAG.getSetCC(TLI.getSetCCResultType(NVT), Lo,
                                    DAG.getConstant(0, NVT), ISD::SETNE);
 
   SDValue LoLZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
@@ -2007,15 +2019,16 @@ void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
   // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
   TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
   SDValue Tmp1, Tmp2;
-  Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC,
-                           false, DagCombineInfo);
+  Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
+                           LHSLo, RHSLo, LowCC, false, DagCombineInfo);
   if (!Tmp1.getNode())
-    Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
-  Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
-                           CCCode, false, DagCombineInfo);
+    Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
+                        LHSLo, RHSLo, LowCC);
+  Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
+                           LHSHi, RHSHi, CCCode, false, DagCombineInfo);
   if (!Tmp2.getNode())
-    Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
-                       DAG.getCondCode(CCCode));
+    Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi.getValueType()),
+                       LHSHi, RHSHi, DAG.getCondCode(CCCode));
 
   ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
   ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
@@ -2034,11 +2047,11 @@ void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
     return;
   }
 
-  NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
-                             ISD::SETEQ, false, DagCombineInfo);
+  NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
+                             LHSHi, RHSHi, ISD::SETEQ, false, DagCombineInfo);
   if (!NewLHS.getNode())
-    NewLHS = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
-                          ISD::SETEQ);
+    NewLHS = DAG.getSetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
+                          LHSHi, RHSHi, ISD::SETEQ);
   NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
                        NewLHS, Tmp1, Tmp2);
   NewRHS = SDValue();
@@ -2223,8 +2236,8 @@ SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
     // Check whether the sign bit is set.
     SDValue Lo, Hi;
     GetExpandedInteger(Op, Lo, Hi);
-    SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
-                                   DAG.getConstant(0, Hi.getValueType()),
+    SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi.getValueType()),
+                                   Hi, DAG.getConstant(0, Hi.getValueType()),
                                    ISD::SETLT);
 
     // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 5c34db489b8..39b517961d9 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -216,7 +216,7 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
   SDValue LHS = GetScalarizedVector(N->getOperand(0));
   SDValue RHS = GetScalarizedVector(N->getOperand(1));
   MVT NVT = N->getValueType(0).getVectorElementType();
-  MVT SVT = TLI.getSetCCResultType(LHS);
+  MVT SVT = TLI.getSetCCResultType(LHS.getValueType());
 
   // Turn it into a scalar SETCC.
   SDValue Res = DAG.getNode(ISD::SETCC, SVT, LHS, RHS, N->getOperand(2));
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
index a321bed8e36..3daa79ed71d 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
@@ -1369,7 +1369,7 @@ void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT,
   // Emit the range check for the jump table, and branch to the default block
   // for the switch statement if the value being switched on exceeds the largest
   // case in the switch.
-  SDValue CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
+  SDValue CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB.getValueType()), SUB,
                              DAG.getConstant(JTH.Last-JTH.First,VT),
                              ISD::SETUGT);
 
@@ -1402,7 +1402,7 @@ void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) {
                             DAG.getConstant(B.First, VT));
 
   // Check range
-  SDValue RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
+  SDValue RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB.getValueType()), SUB,
                                   DAG.getConstant(B.Range, VT),
                                   ISD::SETUGT);
 
@@ -1455,8 +1455,8 @@ void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
 
   SDValue AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), SwitchVal,
                               DAG.getConstant(B.Mask, TLI.getPointerTy()));
-  SDValue AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp), AndOp,
-                                DAG.getConstant(0, TLI.getPointerTy()),
+  SDValue AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp.getValueType()),
+                                AndOp, DAG.getConstant(0, TLI.getPointerTy()),
                                 ISD::SETNE);
 
   CurMBB->addSuccessor(B.TargetBB);
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index f2800bf6860..6fcecc872b5 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -607,7 +607,7 @@ const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
 }
 
 
-MVT TargetLowering::getSetCCResultType(const SDValue &) const {
+MVT TargetLowering::getSetCCResultType(MVT VT) const {
   return getValueType(TD->getIntPtrType());
 }
 
diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp
index 7b0fcca9a37..793d475e0dd 100644
--- a/lib/Target/Alpha/AlphaISelLowering.cpp
+++ b/lib/Target/Alpha/AlphaISelLowering.cpp
@@ -159,7 +159,7 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
   computeRegisterProperties();
 }
 
-MVT AlphaTargetLowering::getSetCCResultType(const SDValue &) const {
+MVT AlphaTargetLowering::getSetCCResultType(MVT VT) const {
   return MVT::i64;
 }
 
diff --git a/lib/Target/Alpha/AlphaISelLowering.h b/lib/Target/Alpha/AlphaISelLowering.h
index a29a518a102..cebd3ac998a 100644
--- a/lib/Target/Alpha/AlphaISelLowering.h
+++ b/lib/Target/Alpha/AlphaISelLowering.h
@@ -67,7 +67,7 @@ namespace llvm {
     explicit AlphaTargetLowering(TargetMachine &TM);
     
     /// getSetCCResultType - Get the SETCC result ValueType
-    virtual MVT getSetCCResultType(const SDValue &) const;
+    virtual MVT getSetCCResultType(MVT VT) const;
 
     /// LowerOperation - Provide custom lowering hooks for some operations.
     ///
diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp
index 5ccfd14aa4b..a0c667847e2 100644
--- a/lib/Target/CellSPU/SPUISelLowering.cpp
+++ b/lib/Target/CellSPU/SPUISelLowering.cpp
@@ -433,8 +433,7 @@ SPUTargetLowering::getTargetNodeName(unsigned Opcode) const
 // Return the Cell SPU's SETCC result type
 //===----------------------------------------------------------------------===//
 
-MVT SPUTargetLowering::getSetCCResultType(const SDValue &Op) const {
-  MVT VT = Op.getValueType();
+MVT SPUTargetLowering::getSetCCResultType(MVT VT) const {
   // i16 and i32 are valid SETCC result types
   return ((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) ? VT : MVT::i32);
 }
@@ -2510,7 +2509,8 @@ static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
   // legalizer insists on combining SETCC/SELECT into SELECT_CC, so we end up
   // with another "cannot select select_cc" assert:
 
-  SDValue compare = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op),
+  SDValue compare = DAG.getNode(ISD::SETCC,
+                                TLI.getSetCCResultType(Op.getValueType()),
                                 lhs, rhs, condition);
   return DAG.getNode(SPUISD::SELB, VT, falseval, trueval, compare);
 }
diff --git a/lib/Target/CellSPU/SPUISelLowering.h b/lib/Target/CellSPU/SPUISelLowering.h
index 0eed9b0cfc5..feee6fd55c1 100644
--- a/lib/Target/CellSPU/SPUISelLowering.h
+++ b/lib/Target/CellSPU/SPUISelLowering.h
@@ -95,7 +95,7 @@ namespace llvm {
     virtual const char *getTargetNodeName(unsigned Opcode) const;
 
     /// getSetCCResultType - Return the ValueType for ISD::SETCC
-    virtual MVT getSetCCResultType(const SDValue &) const;
+    virtual MVT getSetCCResultType(MVT VT) const;
 
     //! Custom lowering hooks
     virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp
index 11582719c80..c40f89d7f0d 100644
--- a/lib/Target/IA64/IA64ISelLowering.cpp
+++ b/lib/Target/IA64/IA64ISelLowering.cpp
@@ -140,7 +140,7 @@ const char *IA64TargetLowering::getTargetNodeName(unsigned Opcode) const {
   }
 }
   
-MVT IA64TargetLowering::getSetCCResultType(const SDValue &) const {
+MVT IA64TargetLowering::getSetCCResultType(MVT VT) const {
   return MVT::i1;
 }
 
diff --git a/lib/Target/IA64/IA64ISelLowering.h b/lib/Target/IA64/IA64ISelLowering.h
index b8b876c51b7..9b0854fb893 100644
--- a/lib/Target/IA64/IA64ISelLowering.h
+++ b/lib/Target/IA64/IA64ISelLowering.h
@@ -49,7 +49,7 @@ namespace llvm {
     const char *getTargetNodeName(unsigned Opcode) const;
 
     /// getSetCCResultType: return ISD::SETCC's result type.
-    virtual MVT getSetCCResultType(const SDValue &) const;
+    virtual MVT getSetCCResultType(MVT VT) const;
       
     /// LowerArguments - This hook must be implemented to indicate how we should
     /// lower the arguments for the specified function, into the specified DAG.
diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp
index bc0294f4a02..e636e7807a1 100644
--- a/lib/Target/Mips/MipsISelLowering.cpp
+++ b/lib/Target/Mips/MipsISelLowering.cpp
@@ -152,7 +152,7 @@ MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
 }
 
 
-MVT MipsTargetLowering::getSetCCResultType(const SDValue &) const {
+MVT MipsTargetLowering::getSetCCResultType(MVT VT) const {
   return MVT::i32;
 }
 
diff --git a/lib/Target/Mips/MipsISelLowering.h b/lib/Target/Mips/MipsISelLowering.h
index 5704b7ef8e2..decaae1d9da 100644
--- a/lib/Target/Mips/MipsISelLowering.h
+++ b/lib/Target/Mips/MipsISelLowering.h
@@ -79,7 +79,7 @@ namespace llvm {
     virtual const char *getTargetNodeName(unsigned Opcode) const;
 
     /// getSetCCResultType - get the ISD::SETCC result ValueType
-    MVT getSetCCResultType(const SDValue &) const;
+    MVT getSetCCResultType(MVT VT) const;
 
   private:
     // Subtarget Info
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 58fd67505f7..9170f61f0fe 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -432,7 +432,7 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
 }
 
 
-MVT PPCTargetLowering::getSetCCResultType(const SDValue &) const {
+MVT PPCTargetLowering::getSetCCResultType(MVT VT) const {
   return MVT::i32;
 }
 
diff --git a/lib/Target/PowerPC/PPCISelLowering.h b/lib/Target/PowerPC/PPCISelLowering.h
index 8fa79724931..75dd758abe8 100644
--- a/lib/Target/PowerPC/PPCISelLowering.h
+++ b/lib/Target/PowerPC/PPCISelLowering.h
@@ -231,7 +231,7 @@ namespace llvm {
     virtual const char *getTargetNodeName(unsigned Opcode) const;
 
     /// getSetCCResultType - Return the ISD::SETCC ValueType
-    virtual MVT getSetCCResultType(const SDValue &) const;
+    virtual MVT getSetCCResultType(MVT VT) const;
 
     /// getPreIndexedAddressParts - returns true by value, base pointer and
     /// offset pointer and addressing mode by reference if the node's address
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 515adf40842..43a7bb5bb5b 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -819,7 +819,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
 }
 
 
-MVT X86TargetLowering::getSetCCResultType(const SDValue &) const {
+MVT X86TargetLowering::getSetCCResultType(MVT VT) const {
   return MVT::i8;
 }
 
diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h
index cd6ab000834..37d126e6d39 100644
--- a/lib/Target/X86/X86ISelLowering.h
+++ b/lib/Target/X86/X86ISelLowering.h
@@ -400,7 +400,7 @@ namespace llvm {
     virtual const char *getTargetNodeName(unsigned Opcode) const;
 
     /// getSetCCResultType - Return the ISD::SETCC ValueType
-    virtual MVT getSetCCResultType(const SDValue &) const;
+    virtual MVT getSetCCResultType(MVT VT) const;
 
     /// computeMaskedBitsForTargetNode - Determine which of the bits specified 
     /// in Mask are known to be either zero or one and return them in the 
diff --git a/test/CodeGen/CellSPU/2009-01-01-BrCond.ll b/test/CodeGen/CellSPU/2009-01-01-BrCond.ll
new file mode 100644
index 00000000000..5417c5f9bb2
--- /dev/null
+++ b/test/CodeGen/CellSPU/2009-01-01-BrCond.ll
@@ -0,0 +1,31 @@
+; RUN: llvm-as < %s | llc -march=cellspu -o - | grep brnz
+; PR3274
+
+target datalayout = "E-p:32:32:128-i1:8:128-i8:8:128-i16:16:128-i32:32:128-i64:32:128-f32:32:128-f64:64:128-v64:64:64-v128:128:128-a0:0:128-s0:128:128"
+target triple = "spu"
+	%struct.anon = type { i64 }
+	%struct.fp_number_type = type { i32, i32, i32, [4 x i8], %struct.anon }
+
+define double @__floatunsidf(i32 %arg_a) nounwind {
+entry:
+	%in = alloca %struct.fp_number_type, align 8		; <%struct.fp_number_type*> [#uses=5]
+	%0 = getelementptr %struct.fp_number_type* %in, i32 0, i32 1		; <i32*> [#uses=1]
+	store i32 0, i32* %0, align 4
+	%1 = icmp eq i32 %arg_a, 0		; <i1> [#uses=1]
+	%2 = getelementptr %struct.fp_number_type* %in, i32 0, i32 0		; <i32*> [#uses=2]
+	br i1 %1, label %bb, label %bb1
+
+bb:		; preds = %entry
+	store i32 2, i32* %2, align 8
+	br label %bb7
+
+bb1:		; preds = %entry
+	ret double 0.0
+
+bb7:		; preds = %bb5, %bb1, %bb
+	ret double 1.0
+}
+
+declare i32 @llvm.ctlz.i32(i32) nounwind readnone
+
+declare double @__pack_d(%struct.fp_number_type*)