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https://github.com/c64scene-ar/llvm-6502.git
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Extract spill cost calculation to a new method, and use definePhysReg() to clear
out aliases when allocating. Clean up allocVirtReg(). Use calcSpillCost() to allow more aggressive hinting. Now the hint is always taken unless blocked by a reserved register. This leads to more coalescing, lower register pressure, and less spilling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103939 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
parent
bae5210321
commit
548643c573
@ -118,6 +118,11 @@ namespace {
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// not be erased.
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bool isBulkSpilling;
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enum {
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spillClean = 1,
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spillDirty = 100,
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spillImpossible = ~0u
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};
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public:
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virtual const char *getPassName() const {
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return "Fast Register Allocator";
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@ -144,6 +149,7 @@ namespace {
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void usePhysReg(MachineOperand&);
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void definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState);
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unsigned calcSpillCost(unsigned PhysReg) const;
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void assignVirtToPhysReg(LiveRegEntry &LRE, unsigned PhysReg);
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void allocVirtReg(MachineInstr *MI, LiveRegEntry &LRE, unsigned Hint);
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LiveRegMap::iterator defineVirtReg(MachineInstr *MI, unsigned OpNum,
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@ -369,6 +375,44 @@ void RAFast::definePhysReg(MachineInstr *MI, unsigned PhysReg,
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}
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// calcSpillCost - Return the cost of spilling clearing out PhysReg and
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// aliases so it is free for allocation.
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// Returns 0 when PhysReg is free or disabled with all aliases disabled - it
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// can be allocated directly.
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// Returns spillImpossible when PhysReg or an alias can't be spilled.
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unsigned RAFast::calcSpillCost(unsigned PhysReg) const {
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switch (unsigned VirtReg = PhysRegState[PhysReg]) {
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case regDisabled:
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break;
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case regFree:
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return 0;
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case regReserved:
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return spillImpossible;
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default:
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return LiveVirtRegs.lookup(VirtReg).Dirty ? spillDirty : spillClean;
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}
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// This is a disabled register, add up const of aliases.
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unsigned Cost = 0;
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for (const unsigned *AS = TRI->getAliasSet(PhysReg);
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unsigned Alias = *AS; ++AS) {
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switch (unsigned VirtReg = PhysRegState[Alias]) {
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case regDisabled:
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break;
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case regFree:
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++Cost;
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break;
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case regReserved:
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return spillImpossible;
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default:
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Cost += LiveVirtRegs.lookup(VirtReg).Dirty ? spillDirty : spillClean;
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break;
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}
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}
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return Cost;
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}
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/// assignVirtToPhysReg - This method updates local state so that we know
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/// that PhysReg is the proper container for VirtReg now. The physical
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/// register must not be used for anything else when this is called.
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@ -383,15 +427,12 @@ void RAFast::assignVirtToPhysReg(LiveRegEntry &LRE, unsigned PhysReg) {
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/// allocVirtReg - Allocate a physical register for VirtReg.
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void RAFast::allocVirtReg(MachineInstr *MI, LiveRegEntry &LRE, unsigned Hint) {
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const unsigned SpillCost = 100;
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const unsigned VirtReg = LRE.first;
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assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
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"Can only allocate virtual registers");
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const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
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TargetRegisterClass::iterator AOB = RC->allocation_order_begin(*MF);
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TargetRegisterClass::iterator AOE = RC->allocation_order_end(*MF);
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// Ignore invalid hints.
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if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) ||
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@ -403,107 +444,44 @@ void RAFast::allocVirtReg(MachineInstr *MI, LiveRegEntry &LRE, unsigned Hint) {
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if (Hint) {
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assert(RC->contains(Hint) && !UsedInInstr.test(Hint) &&
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Allocatable.test(Hint) && "Invalid hint should have been cleared");
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switch(PhysRegState[Hint]) {
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case regDisabled:
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case regReserved:
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break;
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switch(calcSpillCost(Hint)) {
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default:
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spillVirtReg(MI, PhysRegState[Hint]);
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definePhysReg(MI, Hint, regFree);
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// Fall through.
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case regFree:
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case 0:
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return assignVirtToPhysReg(LRE, Hint);
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case spillImpossible:
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break;
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}
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}
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TargetRegisterClass::iterator AOB = RC->allocation_order_begin(*MF);
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TargetRegisterClass::iterator AOE = RC->allocation_order_end(*MF);
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// First try to find a completely free register.
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unsigned BestCost = 0, BestReg = 0;
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bool hasDisabled = false;
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for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) {
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unsigned PhysReg = *I;
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switch(PhysRegState[PhysReg]) {
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case regDisabled:
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hasDisabled = true;
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case regReserved:
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continue;
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case regFree:
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if (!UsedInInstr.test(PhysReg))
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return assignVirtToPhysReg(LRE, PhysReg);
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continue;
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default:
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// Grab the first spillable register we meet.
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if (!BestReg && !UsedInInstr.test(PhysReg))
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BestReg = PhysReg, BestCost = SpillCost;
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continue;
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}
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if (PhysRegState[PhysReg] == regFree && !UsedInInstr.test(PhysReg))
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return assignVirtToPhysReg(LRE, PhysReg);
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}
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DEBUG(dbgs() << "Allocating %reg" << VirtReg << " from " << RC->getName()
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<< " candidate=" << TRI->getName(BestReg) << "\n");
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<< "\n");
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// Try to extend the working set for RC if there were any disabled registers.
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if (hasDisabled && (!BestReg || BestCost >= SpillCost)) {
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for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) {
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unsigned PhysReg = *I;
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if (PhysRegState[PhysReg] != regDisabled || UsedInInstr.test(PhysReg))
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continue;
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// Calculate the cost of bringing PhysReg into the working set.
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unsigned Cost=0;
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bool Impossible = false;
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for (const unsigned *AS = TRI->getAliasSet(PhysReg);
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unsigned Alias = *AS; ++AS) {
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if (UsedInInstr.test(Alias)) {
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Impossible = true;
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break;
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}
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switch (PhysRegState[Alias]) {
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case regDisabled:
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break;
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case regReserved:
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Impossible = true;
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break;
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case regFree:
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Cost++;
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break;
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default:
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Cost += SpillCost;
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break;
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}
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}
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if (Impossible) continue;
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DEBUG(dbgs() << "- candidate " << TRI->getName(PhysReg)
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<< " cost=" << Cost << "\n");
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if (!BestReg || Cost < BestCost) {
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BestReg = PhysReg;
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BestCost = Cost;
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if (Cost < SpillCost) break;
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}
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unsigned BestReg = 0, BestCost = spillImpossible;
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for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) {
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unsigned Cost = calcSpillCost(*I);
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if (Cost < BestCost) {
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BestReg = *I;
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BestCost = Cost;
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if (Cost == 0) break;
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}
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}
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if (BestReg) {
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// BestCost is 0 when all aliases are already disabled.
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if (BestCost) {
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if (PhysRegState[BestReg] != regDisabled)
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spillVirtReg(MI, PhysRegState[BestReg]);
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else {
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// Make sure all aliases are disabled.
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for (const unsigned *AS = TRI->getAliasSet(BestReg);
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unsigned Alias = *AS; ++AS) {
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switch (PhysRegState[Alias]) {
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case regDisabled:
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continue;
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case regFree:
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PhysRegState[Alias] = regDisabled;
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break;
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default:
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spillVirtReg(MI, PhysRegState[Alias]);
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PhysRegState[Alias] = regDisabled;
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break;
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}
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}
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}
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}
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if (BestCost)
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definePhysReg(MI, BestReg, regFree);
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return assignVirtToPhysReg(LRE, BestReg);
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}
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