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- More pre-split fixes: spill slot live interval computation bug; restore point bug.
- If a def is spilt, remember its spill index to allow its reuse. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58375 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -156,6 +156,8 @@ namespace llvm {
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return reg & ~(1U << (sizeof(unsigned)*8-1));
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return reg & ~(1U << (sizeof(unsigned)*8-1));
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}
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}
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bool hasAtLeastOneValue() const { return !valnos.empty(); }
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bool containsOneValue() const { return valnos.size() == 1; }
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bool containsOneValue() const { return valnos.size() == 1; }
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unsigned getNumValNums() const { return (unsigned)valnos.size(); }
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unsigned getNumValNums() const { return (unsigned)valnos.size(); }
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@ -30,6 +30,7 @@
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/DepthFirstIterator.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/Statistic.h"
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using namespace llvm;
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using namespace llvm;
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@ -69,8 +70,8 @@ namespace {
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// IntervalSSMap - A map from live interval to spill slots.
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// IntervalSSMap - A map from live interval to spill slots.
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DenseMap<unsigned, int> IntervalSSMap;
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DenseMap<unsigned, int> IntervalSSMap;
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// RestoreMIs - All the restores inserted due to live interval splitting.
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// Def2SpillMap - A map from a def instruction index to spill index.
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SmallPtrSet<MachineInstr*, 8> RestoreMIs;
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DenseMap<unsigned, unsigned> Def2SpillMap;
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public:
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public:
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static char ID;
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static char ID;
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@ -93,7 +94,7 @@ namespace {
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virtual void releaseMemory() {
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virtual void releaseMemory() {
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IntervalSSMap.clear();
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IntervalSSMap.clear();
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RestoreMIs.clear();
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Def2SpillMap.clear();
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}
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}
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virtual const char *getPassName() const {
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virtual const char *getPassName() const {
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@ -124,7 +125,8 @@ namespace {
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int CreateSpillStackSlot(unsigned, const TargetRegisterClass *);
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int CreateSpillStackSlot(unsigned, const TargetRegisterClass *);
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bool IsAvailableInStack(unsigned, unsigned, int&) const;
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bool IsAvailableInStack(MachineBasicBlock*, unsigned, unsigned, unsigned,
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unsigned&, int&) const;
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void UpdateSpillSlotInterval(VNInfo*, unsigned, unsigned);
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void UpdateSpillSlotInterval(VNInfo*, unsigned, unsigned);
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@ -221,6 +223,8 @@ PreAllocSplitting::findRestorePoint(MachineBasicBlock *MBB, MachineInstr *MI,
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unsigned LastIdx,
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unsigned LastIdx,
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SmallPtrSet<MachineInstr*, 4> &RefsInMBB,
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SmallPtrSet<MachineInstr*, 4> &RefsInMBB,
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unsigned &RestoreIndex) {
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unsigned &RestoreIndex) {
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// FIXME: Allow spill to be inserted to the beginning of the mbb. Update mbb
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// begin index accordingly.
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MachineBasicBlock::iterator Pt = MBB->end();
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MachineBasicBlock::iterator Pt = MBB->end();
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unsigned EndIdx = LIs->getMBBEndIdx(MBB);
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unsigned EndIdx = LIs->getMBBEndIdx(MBB);
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@ -229,8 +233,8 @@ PreAllocSplitting::findRestorePoint(MachineBasicBlock *MBB, MachineInstr *MI,
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if (RefsInMBB.empty() && LastIdx >= EndIdx) {
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if (RefsInMBB.empty() && LastIdx >= EndIdx) {
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MachineBasicBlock::iterator MII = MBB->end();
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MachineBasicBlock::iterator MII = MBB->end();
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MachineBasicBlock::iterator EndPt = MI;
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MachineBasicBlock::iterator EndPt = MI;
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--MII;
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do {
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do {
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--MII;
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unsigned Index = LIs->getInstructionIndex(MII);
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unsigned Index = LIs->getInstructionIndex(MII);
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unsigned Gap = LIs->findGapBeforeInstr(Index);
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unsigned Gap = LIs->findGapBeforeInstr(Index);
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if (Gap) {
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if (Gap) {
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@ -238,6 +242,7 @@ PreAllocSplitting::findRestorePoint(MachineBasicBlock *MBB, MachineInstr *MI,
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RestoreIndex = Gap;
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RestoreIndex = Gap;
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break;
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break;
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}
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}
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--MII;
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} while (MII != EndPt);
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} while (MII != EndPt);
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} else {
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} else {
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MachineBasicBlock::iterator MII = MI;
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MachineBasicBlock::iterator MII = MI;
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@ -278,7 +283,7 @@ int PreAllocSplitting::CreateSpillStackSlot(unsigned Reg,
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// Create live interval for stack slot.
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// Create live interval for stack slot.
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CurrSLI = &LSs->getOrCreateInterval(SS);
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CurrSLI = &LSs->getOrCreateInterval(SS);
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if (CurrSLI->getNumValNums())
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if (CurrSLI->hasAtLeastOneValue())
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CurrSValNo = CurrSLI->getValNumInfo(0);
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CurrSValNo = CurrSLI->getValNumInfo(0);
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else
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else
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CurrSValNo = CurrSLI->getNextValue(~0U, 0, LSs->getVNInfoAllocator());
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CurrSValNo = CurrSLI->getNextValue(~0U, 0, LSs->getVNInfoAllocator());
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@ -288,15 +293,30 @@ int PreAllocSplitting::CreateSpillStackSlot(unsigned Reg,
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/// IsAvailableInStack - Return true if register is available in a split stack
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/// IsAvailableInStack - Return true if register is available in a split stack
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/// slot at the specified index.
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/// slot at the specified index.
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bool
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bool
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PreAllocSplitting::IsAvailableInStack(unsigned Reg, unsigned Index, int &SS) const {
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PreAllocSplitting::IsAvailableInStack(MachineBasicBlock *DefMBB,
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unsigned Reg, unsigned DefIndex,
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unsigned RestoreIndex, unsigned &SpillIndex,
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int& SS) const {
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if (!DefMBB)
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return false;
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DenseMap<unsigned, int>::iterator I = IntervalSSMap.find(Reg);
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DenseMap<unsigned, int>::iterator I = IntervalSSMap.find(Reg);
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if (I == IntervalSSMap.end())
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if (I == IntervalSSMap.end())
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return false;
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return false;
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if (LSs->getInterval(I->second).liveAt(Index)) {
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DenseMap<unsigned, unsigned>::iterator II = Def2SpillMap.find(DefIndex);
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SS = I->second;
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if (II == Def2SpillMap.end())
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return true;
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return false;
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}
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return false;
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// If last spill of def is in the same mbb as barrier mbb (where restore will
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// be), make sure it's not below the intended restore index.
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// FIXME: Undo the previous spill?
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assert(LIs->getMBBFromIndex(II->second) == DefMBB);
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if (DefMBB == BarrierMBB && II->second >= RestoreIndex)
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return false;
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SS = I->second;
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SpillIndex = II->second;
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return true;
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}
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}
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/// UpdateSpillSlotInterval - Given the specified val# of the register live
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/// UpdateSpillSlotInterval - Given the specified val# of the register live
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@ -305,48 +325,58 @@ PreAllocSplitting::IsAvailableInStack(unsigned Reg, unsigned Index, int &SS) con
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void
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void
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PreAllocSplitting::UpdateSpillSlotInterval(VNInfo *ValNo, unsigned SpillIndex,
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PreAllocSplitting::UpdateSpillSlotInterval(VNInfo *ValNo, unsigned SpillIndex,
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unsigned RestoreIndex) {
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unsigned RestoreIndex) {
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const LiveRange *LR = CurrLI->getLiveRangeContaining(SpillIndex);
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assert(LIs->getMBBFromIndex(RestoreIndex) == BarrierMBB &&
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if (LR->contains(RestoreIndex)) {
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"Expect restore in the barrier mbb");
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MachineBasicBlock *MBB = LIs->getMBBFromIndex(SpillIndex);
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if (MBB == BarrierMBB) {
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// Intra-block spill + restore. We are done.
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LiveRange SLR(SpillIndex, RestoreIndex, CurrSValNo);
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LiveRange SLR(SpillIndex, RestoreIndex, CurrSValNo);
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CurrSLI->addRange(SLR);
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CurrSLI->addRange(SLR);
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return;
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return;
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}
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}
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SmallPtrSet<const LiveRange*, 4> Processed;
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SmallPtrSet<MachineBasicBlock*, 4> Processed;
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LiveRange SLR(SpillIndex, LR->end, CurrSValNo);
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unsigned EndIdx = LIs->getMBBEndIdx(MBB);
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LiveRange SLR(SpillIndex, EndIdx+1, CurrSValNo);
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CurrSLI->addRange(SLR);
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CurrSLI->addRange(SLR);
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Processed.insert(LR);
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Processed.insert(MBB);
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// Start from the spill mbb, figure out the extend of the spill slot's
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// Start from the spill mbb, figure out the extend of the spill slot's
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// live interval.
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// live interval.
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SmallVector<MachineBasicBlock*, 4> WorkList;
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SmallVector<MachineBasicBlock*, 4> WorkList;
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MachineBasicBlock *MBB = LIs->getMBBFromIndex(SpillIndex);
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const LiveRange *LR = CurrLI->getLiveRangeContaining(SpillIndex);
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if (LR->end > LIs->getMBBEndIdx(MBB))
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if (LR->end > EndIdx)
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// If live range extend beyond end of mbb, add successors to work list.
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// If live range extend beyond end of mbb, add successors to work list.
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for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
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for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
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SE = MBB->succ_end(); SI != SE; ++SI)
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SE = MBB->succ_end(); SI != SE; ++SI)
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WorkList.push_back(*SI);
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WorkList.push_back(*SI);
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// Live range may cross multiple basic blocks, add all reachable mbbs to
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// the work list.
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LIs->findReachableMBBs(LR->start, LR->end, WorkList);
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while (!WorkList.empty()) {
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while (!WorkList.empty()) {
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MachineBasicBlock *MBB = WorkList.back();
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MachineBasicBlock *MBB = WorkList.back();
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WorkList.pop_back();
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WorkList.pop_back();
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if (Processed.count(MBB))
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continue;
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unsigned Idx = LIs->getMBBStartIdx(MBB);
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unsigned Idx = LIs->getMBBStartIdx(MBB);
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LR = CurrLI->getLiveRangeContaining(Idx);
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LR = CurrLI->getLiveRangeContaining(Idx);
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if (LR && LR->valno == ValNo && !Processed.count(LR)) {
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if (LR && LR->valno == ValNo) {
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if (LR->contains(RestoreIndex)) {
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EndIdx = LIs->getMBBEndIdx(MBB);
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if (Idx <= RestoreIndex && RestoreIndex < EndIdx) {
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// Spill slot live interval stops at the restore.
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// Spill slot live interval stops at the restore.
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LiveRange SLR(LR->start, RestoreIndex, CurrSValNo);
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LiveRange SLR(Idx, RestoreIndex, CurrSValNo);
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CurrSLI->addRange(SLR);
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CurrSLI->addRange(SLR);
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LIs->findReachableMBBs(LR->start, RestoreIndex, WorkList);
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} else if (LR->end > EndIdx) {
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// Live range extends beyond end of mbb, process successors.
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LiveRange SLR(Idx, EndIdx+1, CurrSValNo);
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CurrSLI->addRange(SLR);
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for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
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SE = MBB->succ_end(); SI != SE; ++SI)
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WorkList.push_back(*SI);
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} else {
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} else {
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LiveRange SLR(LR->start, LR->end, CurrSValNo);
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LiveRange SLR(Idx, LR->end, CurrSValNo);
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CurrSLI->addRange(SLR);
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CurrSLI->addRange(SLR);
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LIs->findReachableMBBs(LR->start, LR->end, WorkList);
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}
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}
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Processed.insert(LR);
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Processed.insert(MBB);
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}
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}
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}
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}
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}
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}
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@ -357,6 +387,9 @@ PreAllocSplitting::UpdateSpillSlotInterval(VNInfo *ValNo, unsigned SpillIndex,
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void
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void
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PreAllocSplitting::UpdateRegisterInterval(VNInfo *ValNo, unsigned SpillIndex,
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PreAllocSplitting::UpdateRegisterInterval(VNInfo *ValNo, unsigned SpillIndex,
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unsigned RestoreIndex) {
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unsigned RestoreIndex) {
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assert(LIs->getMBBFromIndex(RestoreIndex) == BarrierMBB &&
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"Expect restore in the barrier mbb");
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SmallVector<std::pair<unsigned,unsigned>, 4> Before;
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SmallVector<std::pair<unsigned,unsigned>, 4> Before;
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SmallVector<std::pair<unsigned,unsigned>, 4> After;
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SmallVector<std::pair<unsigned,unsigned>, 4> After;
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SmallVector<unsigned, 4> BeforeKills;
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SmallVector<unsigned, 4> BeforeKills;
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@ -380,7 +413,7 @@ PreAllocSplitting::UpdateRegisterInterval(VNInfo *ValNo, unsigned SpillIndex,
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// Start from the restore mbb, figure out what part of the live interval
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// Start from the restore mbb, figure out what part of the live interval
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// are defined by the restore.
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// are defined by the restore.
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SmallVector<MachineBasicBlock*, 4> WorkList;
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SmallVector<MachineBasicBlock*, 4> WorkList;
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MachineBasicBlock *MBB = LIs->getMBBFromIndex(RestoreIndex);
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MachineBasicBlock *MBB = BarrierMBB;
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for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
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for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
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SE = MBB->succ_end(); SI != SE; ++SI)
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SE = MBB->succ_end(); SI != SE; ++SI)
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WorkList.push_back(*SI);
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WorkList.push_back(*SI);
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@ -547,7 +580,6 @@ PreAllocSplitting::ShrinkWrapLiveInterval(VNInfo *ValNo, MachineBasicBlock *MBB,
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} else if (MBB == DefMBB) {
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} else if (MBB == DefMBB) {
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// There are no uses after the def.
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// There are no uses after the def.
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MachineInstr *DefMI = LIs->getInstructionFromIndex(ValNo->def);
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MachineInstr *DefMI = LIs->getInstructionFromIndex(ValNo->def);
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assert(RestoreMIs.count(DefMI) && "Not defined by a join?");
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if (UseMBBs.empty()) {
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if (UseMBBs.empty()) {
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// The only use must be below barrier in the barrier block. It's safe to
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// The only use must be below barrier in the barrier block. It's safe to
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// remove the def.
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// remove the def.
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@ -641,7 +673,8 @@ bool PreAllocSplitting::SplitRegLiveInterval(LiveInterval *LI) {
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TII->storeRegToStackSlot(*BarrierMBB, SpillPt, CurrLI->reg, true, SS, RC);
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TII->storeRegToStackSlot(*BarrierMBB, SpillPt, CurrLI->reg, true, SS, RC);
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SpillMI = prior(SpillPt);
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SpillMI = prior(SpillPt);
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LIs->InsertMachineInstrInMaps(SpillMI, SpillIndex);
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LIs->InsertMachineInstrInMaps(SpillMI, SpillIndex);
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} else if (!IsAvailableInStack(CurrLI->reg, RestoreIndex, SS)) {
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} else if (!IsAvailableInStack(DefMBB, CurrLI->reg, ValNo->def,
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RestoreIndex, SpillIndex, SS)) {
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// If it's already split, just restore the value. There is no need to spill
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// If it's already split, just restore the value. There is no need to spill
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// the def again.
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// the def again.
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if (!DefMI)
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if (!DefMI)
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@ -667,11 +700,14 @@ bool PreAllocSplitting::SplitRegLiveInterval(LiveInterval *LI) {
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LIs->InsertMachineInstrInMaps(SpillMI, SpillIndex);
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LIs->InsertMachineInstrInMaps(SpillMI, SpillIndex);
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}
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}
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// Remember def instruction index to spill index mapping.
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if (DefMI && SpillMI)
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Def2SpillMap[ValNo->def] = SpillIndex;
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// Add restore.
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// Add restore.
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TII->loadRegFromStackSlot(*BarrierMBB, RestorePt, CurrLI->reg, SS, RC);
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TII->loadRegFromStackSlot(*BarrierMBB, RestorePt, CurrLI->reg, SS, RC);
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MachineInstr *LoadMI = prior(RestorePt);
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MachineInstr *LoadMI = prior(RestorePt);
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LIs->InsertMachineInstrInMaps(LoadMI, RestoreIndex);
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LIs->InsertMachineInstrInMaps(LoadMI, RestoreIndex);
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RestoreMIs.insert(LoadMI);
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// If live interval is spilled in the same block as the barrier, just
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// If live interval is spilled in the same block as the barrier, just
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// create a hole in the interval.
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// create a hole in the interval.
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@ -689,11 +725,8 @@ bool PreAllocSplitting::SplitRegLiveInterval(LiveInterval *LI) {
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}
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}
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// Update spill stack slot live interval.
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// Update spill stack slot live interval.
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if (SpillIndex)
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UpdateSpillSlotInterval(ValNo, LIs->getUseIndex(SpillIndex)+1,
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// If value is already in stack at the restore point, there is
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LIs->getDefIndex(RestoreIndex));
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// no need to update the live interval.
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UpdateSpillSlotInterval(ValNo, LIs->getUseIndex(SpillIndex)+1,
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LIs->getDefIndex(RestoreIndex));
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// Shrink wrap the live interval by walking up the CFG and find the
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// Shrink wrap the live interval by walking up the CFG and find the
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// new kills.
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// new kills.
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@ -795,6 +828,27 @@ bool PreAllocSplitting::runOnMachineFunction(MachineFunction &MF) {
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// Make sure blocks are numbered in order.
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// Make sure blocks are numbered in order.
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MF.RenumberBlocks();
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MF.RenumberBlocks();
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#if 0
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// FIXME: Go top down.
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MachineBasicBlock *Entry = MF.begin();
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SmallPtrSet<MachineBasicBlock*,16> Visited;
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for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*,16> >
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DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited);
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DFI != E; ++DFI) {
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BarrierMBB = *DFI;
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for (MachineBasicBlock::iterator I = BarrierMBB->begin(),
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E = BarrierMBB->end(); I != E; ++I) {
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Barrier = &*I;
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const TargetRegisterClass **BarrierRCs =
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Barrier->getDesc().getRegClassBarriers();
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if (!BarrierRCs)
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continue;
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BarrierIdx = LIs->getInstructionIndex(Barrier);
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MadeChange |= SplitRegLiveIntervals(BarrierRCs);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#else
|
||||||
for (MachineFunction::reverse_iterator I = MF.rbegin(), E = MF.rend();
|
for (MachineFunction::reverse_iterator I = MF.rbegin(), E = MF.rend();
|
||||||
I != E; ++I) {
|
I != E; ++I) {
|
||||||
BarrierMBB = &*I;
|
BarrierMBB = &*I;
|
||||||
@ -809,6 +863,7 @@ bool PreAllocSplitting::runOnMachineFunction(MachineFunction &MF) {
|
|||||||
MadeChange |= SplitRegLiveIntervals(BarrierRCs);
|
MadeChange |= SplitRegLiveIntervals(BarrierRCs);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
return MadeChange;
|
return MadeChange;
|
||||||
}
|
}
|
||||||
|
@ -550,7 +550,7 @@ static void addStackInterval(LiveInterval *cur, LiveStacks *ls_,
|
|||||||
SI.weight += Weight;
|
SI.weight += Weight;
|
||||||
|
|
||||||
VNInfo *VNI;
|
VNInfo *VNI;
|
||||||
if (SI.getNumValNums())
|
if (SI.hasAtLeastOneValue())
|
||||||
VNI = SI.getValNumInfo(0);
|
VNI = SI.getValNumInfo(0);
|
||||||
else
|
else
|
||||||
VNI = SI.getNextValue(~0U, 0, ls_->getVNInfoAllocator());
|
VNI = SI.getNextValue(~0U, 0, ls_->getVNInfoAllocator());
|
||||||
|
51
test/CodeGen/X86/pre-split10.ll
Normal file
51
test/CodeGen/X86/pre-split10.ll
Normal file
@ -0,0 +1,51 @@
|
|||||||
|
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -pre-alloc-split
|
||||||
|
|
||||||
|
define i32 @main(i32 %argc, i8** %argv) nounwind {
|
||||||
|
entry:
|
||||||
|
br label %bb14.i
|
||||||
|
|
||||||
|
bb14.i: ; preds = %bb14.i, %entry
|
||||||
|
%i8.0.reg2mem.0.i = phi i32 [ 0, %entry ], [ %0, %bb14.i ] ; <i32> [#uses=1]
|
||||||
|
%0 = add i32 %i8.0.reg2mem.0.i, 1 ; <i32> [#uses=2]
|
||||||
|
%1 = add double 0.000000e+00, 0.000000e+00 ; <double> [#uses=1]
|
||||||
|
%2 = add double 0.000000e+00, 0.000000e+00 ; <double> [#uses=1]
|
||||||
|
%3 = add double 0.000000e+00, 0.000000e+00 ; <double> [#uses=1]
|
||||||
|
%exitcond75.i = icmp eq i32 %0, 32 ; <i1> [#uses=1]
|
||||||
|
br i1 %exitcond75.i, label %bb24.i, label %bb14.i
|
||||||
|
|
||||||
|
bb24.i: ; preds = %bb14.i
|
||||||
|
%4 = fdiv double 0.000000e+00, 0.000000e+00 ; <double> [#uses=1]
|
||||||
|
%5 = fdiv double %1, 0.000000e+00 ; <double> [#uses=1]
|
||||||
|
%6 = fdiv double %2, 0.000000e+00 ; <double> [#uses=1]
|
||||||
|
%7 = fdiv double %3, 0.000000e+00 ; <double> [#uses=1]
|
||||||
|
br label %bb31.i
|
||||||
|
|
||||||
|
bb31.i: ; preds = %bb31.i, %bb24.i
|
||||||
|
%tmp.0.reg2mem.0.i = phi i32 [ 0, %bb24.i ], [ %indvar.next64.i, %bb31.i ] ; <i32> [#uses=1]
|
||||||
|
%indvar.next64.i = add i32 %tmp.0.reg2mem.0.i, 1 ; <i32> [#uses=2]
|
||||||
|
%exitcond65.i = icmp eq i32 %indvar.next64.i, 64 ; <i1> [#uses=1]
|
||||||
|
br i1 %exitcond65.i, label %bb33.i, label %bb31.i
|
||||||
|
|
||||||
|
bb33.i: ; preds = %bb31.i
|
||||||
|
br label %bb35.preheader.i
|
||||||
|
|
||||||
|
bb5.i.i: ; preds = %bb35.preheader.i
|
||||||
|
%8 = call double @floor(double 0.000000e+00) nounwind readnone ; <double> [#uses=0]
|
||||||
|
br label %bb7.i.i
|
||||||
|
|
||||||
|
bb7.i.i: ; preds = %bb35.preheader.i, %bb5.i.i
|
||||||
|
br label %bb35.preheader.i
|
||||||
|
|
||||||
|
bb35.preheader.i: ; preds = %bb7.i.i, %bb33.i
|
||||||
|
%9 = sub double 0.000000e+00, %4 ; <double> [#uses=1]
|
||||||
|
store double %9, double* null, align 8
|
||||||
|
%10 = sub double 0.000000e+00, %5 ; <double> [#uses=1]
|
||||||
|
store double %10, double* null, align 8
|
||||||
|
%11 = sub double 0.000000e+00, %6 ; <double> [#uses=1]
|
||||||
|
store double %11, double* null, align 8
|
||||||
|
%12 = sub double 0.000000e+00, %7 ; <double> [#uses=1]
|
||||||
|
store double %12, double* null, align 8
|
||||||
|
br i1 false, label %bb7.i.i, label %bb5.i.i
|
||||||
|
}
|
||||||
|
|
||||||
|
declare double @floor(double) nounwind readnone
|
@ -1,5 +1,5 @@
|
|||||||
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -pre-alloc-split -stats |& \
|
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -pre-alloc-split -stats |& \
|
||||||
; RUN: grep {pre-alloc-split} | grep {Number of intervals split} | grep 2
|
; RUN: grep {pre-alloc-split} | grep {Number of intervals split} | grep 1
|
||||||
|
|
||||||
define i32 @t(i32 %arg) {
|
define i32 @t(i32 %arg) {
|
||||||
entry:
|
entry:
|
||||||
|
Loading…
Reference in New Issue
Block a user