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AArch64: remove post-encoder method from FCMP (immediate) instructions.
The work done by the post-encoder (setting architecturally unused bits to 0 as required) can be done by the existing operand that covers the "#0.0". This removes at least one use of the discouraged PostEncoderMethod uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176261 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1945,43 +1945,41 @@ def fpz32 : Operand<f32>,
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ComplexPattern<f32, 1, "SelectFPZeroOperand", [fpimm]> {
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let ParserMatchClass = fpzero_asmoperand;
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let PrintMethod = "printFPZeroOperand";
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let DecoderMethod = "DecodeFPZeroOperand";
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}
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def fpz64 : Operand<f64>,
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ComplexPattern<f64, 1, "SelectFPZeroOperand", [fpimm]> {
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let ParserMatchClass = fpzero_asmoperand;
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let PrintMethod = "printFPZeroOperand";
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let DecoderMethod = "DecodeFPZeroOperand";
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}
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multiclass A64I_fpcmpSignal<bits<2> type, bit imm, dag ins, string asmop2,
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dag pattern> {
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multiclass A64I_fpcmpSignal<bits<2> type, bit imm, dag ins, dag pattern> {
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def _quiet : A64I_fpcmp<0b0, 0b0, type, 0b00, {0b0, imm, 0b0, 0b0, 0b0},
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(outs), ins, !strconcat("fcmp\t$Rn, ", asmop2),
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[pattern], NoItinerary> {
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(outs), ins, "fcmp\t$Rn, $Rm", [pattern],
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NoItinerary> {
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let Defs = [NZCV];
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}
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def _sig : A64I_fpcmp<0b0, 0b0, type, 0b00, {0b1, imm, 0b0, 0b0, 0b0},
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(outs), ins, !strconcat("fcmpe\t$Rn, ", asmop2),
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[], NoItinerary> {
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(outs), ins, "fcmpe\t$Rn, $Rm", [], NoItinerary> {
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let Defs = [NZCV];
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}
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}
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defm FCMPss : A64I_fpcmpSignal<0b00, 0b0, (ins FPR32:$Rn, FPR32:$Rm), "$Rm",
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defm FCMPss : A64I_fpcmpSignal<0b00, 0b0, (ins FPR32:$Rn, FPR32:$Rm),
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(set NZCV, (A64cmp (f32 FPR32:$Rn), FPR32:$Rm))>;
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defm FCMPdd : A64I_fpcmpSignal<0b01, 0b0, (ins FPR64:$Rn, FPR64:$Rm), "$Rm",
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defm FCMPdd : A64I_fpcmpSignal<0b01, 0b0, (ins FPR64:$Rn, FPR64:$Rm),
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(set NZCV, (A64cmp (f64 FPR64:$Rn), FPR64:$Rm))>;
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// What would be Rm should be written as 0, but anything is valid for
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// disassembly so we can't set the bits
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let PostEncoderMethod = "fixFCMPImm" in {
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defm FCMPsi : A64I_fpcmpSignal<0b00, 0b1, (ins FPR32:$Rn, fpz32:$Imm), "$Imm",
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(set NZCV, (A64cmp (f32 FPR32:$Rn), fpz32:$Imm))>;
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// What would be Rm should be written as 0; note that even though it's called
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// "$Rm" here to fit in with the InstrFormats, it's actually an immediate.
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defm FCMPsi : A64I_fpcmpSignal<0b00, 0b1, (ins FPR32:$Rn, fpz32:$Rm),
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(set NZCV, (A64cmp (f32 FPR32:$Rn), fpz32:$Rm))>;
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defm FCMPdi : A64I_fpcmpSignal<0b01, 0b1, (ins FPR64:$Rn, fpz64:$Imm), "$Imm",
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(set NZCV, (A64cmp (f64 FPR64:$Rn), fpz64:$Imm))>;
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}
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defm FCMPdi : A64I_fpcmpSignal<0b01, 0b1, (ins FPR64:$Rn, fpz64:$Rm),
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(set NZCV, (A64cmp (f64 FPR64:$Rn), fpz64:$Rm))>;
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//===----------------------------------------------------------------------===//
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@ -106,6 +106,11 @@ static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeFPZeroOperand(llvm::MCInst &Inst,
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unsigned RmBits,
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uint64_t Address,
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const void *Decoder);
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template<int RegWidth>
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static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst,
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unsigned FullImm,
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@ -381,6 +386,17 @@ static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst,
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFPZeroOperand(llvm::MCInst &Inst,
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unsigned RmBits,
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uint64_t Address,
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const void *Decoder) {
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// Any bits are valid in the instruction (they're architecturally ignored),
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// but a code generator should insert 0.
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Inst.addOperand(MCOperand::CreateImm(0));
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return MCDisassembler::Success;
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}
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template<int RegWidth>
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static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst,
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@ -106,8 +106,6 @@ public:
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void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned fixFCMPImm(const MCInst &MI, unsigned EncodedValue) const;
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template<int hasRs, int hasRt2> unsigned
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fixLoadStoreExclusive(const MCInst &MI, unsigned EncodedValue) const;
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@ -423,15 +421,6 @@ AArch64MCCodeEmitter::getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
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return Result | getAddressWithFixup(UImm16MO, requestedFixup, Fixups);
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}
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unsigned AArch64MCCodeEmitter::fixFCMPImm(const MCInst &MI,
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unsigned EncodedValue) const {
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// For FCMP[E] Rn, #0.0, the Rm field has a canonical representation
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// with 0s, but is architecturally ignored
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EncodedValue &= ~0x1f0000u;
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return EncodedValue;
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}
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template<int hasRs, int hasRt2> unsigned
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AArch64MCCodeEmitter::fixLoadStoreExclusive(const MCInst &MI,
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unsigned EncodedValue) const {
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8
test/MC/Disassembler/AArch64/a64-ignored-fields.txt
Normal file
8
test/MC/Disassembler/AArch64/a64-ignored-fields.txt
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@ -0,0 +1,8 @@
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# RUN: llvm-mc -triple=aarch64 -disassemble -show-encoding < %s | FileCheck %s
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# The "Rm" bits are ignored, but the canonical representation has them filled
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# with 0s. This is what we should produce even if the input bit-pattern had
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# something else there.
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# CHECK: fcmp s31, #0.0 // encoding: [0xe8,0x23,0x20,0x1e]
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0xe8 0x23 0x33 0x1e
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