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https://github.com/c64scene-ar/llvm-6502.git
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Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183490 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -27,12 +27,11 @@ Hexagon_CCState::Hexagon_CCState(CallingConv::ID CC, bool isVarArg,
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const TargetMachine &tm,
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SmallVector<CCValAssign, 16> &locs,
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LLVMContext &c)
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: CallingConv(CC), IsVarArg(isVarArg), TM(tm),
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TRI(*TM.getRegisterInfo()), Locs(locs), Context(c) {
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: CallingConv(CC), IsVarArg(isVarArg), TM(tm), Locs(locs), Context(c) {
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// No stack is used.
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StackOffset = 0;
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UsedRegs.resize((TRI.getNumRegs()+31)/32);
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UsedRegs.resize((TM.getRegisterInfo()->getNumRegs()+31)/32);
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}
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// HandleByVal - Allocate a stack slot large enough to pass an argument by
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@ -56,6 +55,7 @@ void Hexagon_CCState::HandleByVal(unsigned ValNo, EVT ValVT,
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/// MarkAllocated - Mark a register and all of its aliases as allocated.
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void Hexagon_CCState::MarkAllocated(unsigned Reg) {
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const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
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for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
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UsedRegs[*AI/32] |= 1 << (*AI&31);
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}
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@ -48,7 +48,6 @@ class Hexagon_CCState {
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CallingConv::ID CallingConv;
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bool IsVarArg;
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const TargetMachine &TM;
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const TargetRegisterInfo &TRI;
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SmallVector<CCValAssign, 16> &Locs;
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LLVMContext &Context;
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@ -50,15 +50,13 @@ class HexagonDAGToDAGISel : public SelectionDAGISel {
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// Keep a reference to HexagonTargetMachine.
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const HexagonTargetMachine& TM;
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const HexagonInstrInfo *TII;
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DenseMap<const GlobalValue *, unsigned> GlobalAddressUseCountMap;
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public:
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explicit HexagonDAGToDAGISel(const HexagonTargetMachine &targetmachine,
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CodeGenOpt::Level OptLevel)
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: SelectionDAGISel(targetmachine, OptLevel),
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Subtarget(targetmachine.getSubtarget<HexagonSubtarget>()),
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TM(targetmachine),
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TII(static_cast<const HexagonInstrInfo*>(TM.getInstrInfo())) {
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TM(targetmachine) {
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initializeHexagonDAGToDAGISelPass(*PassRegistry::getPassRegistry());
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}
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bool hasNumUsesBelowThresGA(SDNode *N) const;
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@ -444,6 +442,9 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoadSignExtend64(LoadSDNode *LD,
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SDValue N1 = LD->getOperand(1);
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SDValue CPTmpN1_0;
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SDValue CPTmpN1_1;
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const HexagonInstrInfo *TII =
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static_cast<const HexagonInstrInfo*>(TM.getInstrInfo());
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if (SelectADDRriS11_2(N1, CPTmpN1_0, CPTmpN1_1) &&
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N1.getNode()->getValueType(0) == MVT::i32) {
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if (TII->isValidAutoIncImm(LoadedVT, Val)) {
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@ -508,6 +509,9 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoadZeroExtend64(LoadSDNode *LD,
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SDValue N1 = LD->getOperand(1);
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SDValue CPTmpN1_0;
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SDValue CPTmpN1_1;
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const HexagonInstrInfo *TII =
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static_cast<const HexagonInstrInfo*>(TM.getInstrInfo());
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if (SelectADDRriS11_2(N1, CPTmpN1_0, CPTmpN1_1) &&
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N1.getNode()->getValueType(0) == MVT::i32) {
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if (TII->isValidAutoIncImm(LoadedVT, Val)) {
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@ -586,6 +590,8 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, SDLoc dl) {
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bool zextval = (LD->getExtensionType() == ISD::ZEXTLOAD);
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// Figure out the opcode.
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const HexagonInstrInfo *TII =
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static_cast<const HexagonInstrInfo*>(TM.getInstrInfo());
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if (LoadedVT == MVT::i64) {
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if (TII->isValidAutoIncImm(LoadedVT, Val))
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Opcode = Hexagon::POST_LDrid;
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@ -694,6 +700,8 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedStore(StoreSDNode *ST, SDLoc dl) {
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// Offset value must be within representable range
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// and must have correct alignment properties.
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const HexagonInstrInfo *TII =
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static_cast<const HexagonInstrInfo*>(TM.getInstrInfo());
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if (TII->isValidAutoIncImm(StoredVT, Val)) {
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SDValue Ops[] = {Base, CurDAG->getTargetConstant(Val, MVT::i32), Value,
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Chain};
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@ -1207,6 +1215,8 @@ SDNode *HexagonDAGToDAGISel::SelectIntrinsicWOChain(SDNode *N) {
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// We are concerned with only those intrinsics that have predicate registers
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// as at least one of the operands.
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const HexagonInstrInfo *TII =
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static_cast<const HexagonInstrInfo*>(TM.getInstrInfo());
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if (IntrinsicWithPred) {
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SmallVector<SDValue, 8> Ops;
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const MCInstrDesc &MCID = TII->get(IntrinsicWithPred);
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@ -58,7 +58,7 @@ const int Hexagon_MEMB_AUTOINC_MIN = -8;
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HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
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: HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
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RI(ST, *this), Subtarget(ST) {
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RI(ST), Subtarget(ST) {
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}
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@ -27,7 +27,7 @@ namespace llvm {
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class HexagonInstrInfo : public HexagonGenInstrInfo {
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const HexagonRegisterInfo RI;
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const HexagonSubtarget& Subtarget;
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const HexagonSubtarget &Subtarget;
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typedef unsigned Opcode_t;
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public:
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@ -195,7 +195,6 @@ void VLIWMachineScheduler::schedule() {
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void ConvergingVLIWScheduler::initialize(ScheduleDAGMI *dag) {
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DAG = static_cast<VLIWMachineScheduler*>(dag);
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SchedModel = DAG->getSchedModel();
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TRI = DAG->TRI;
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Top.init(DAG, SchedModel);
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Bot.init(DAG, SchedModel);
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@ -409,7 +408,7 @@ void ConvergingVLIWScheduler::traceCandidate(const char *Label,
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SUnit *SU, PressureElement P) {
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dbgs() << Label << " " << Q.getName() << " ";
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if (P.isValid())
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dbgs() << TRI->getRegPressureSetName(P.PSetID) << ":" << P.UnitIncrease
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dbgs() << DAG->TRI->getRegPressureSetName(P.PSetID) << ":" << P.UnitIncrease
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<< " ";
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else
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dbgs() << " ";
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@ -190,7 +190,6 @@ class ConvergingVLIWScheduler : public MachineSchedStrategy {
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VLIWMachineScheduler *DAG;
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const TargetSchedModel *SchedModel;
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const TargetRegisterInfo *TRI;
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// State of the top and bottom scheduled instruction boundaries.
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SchedBoundary Top;
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@ -205,7 +204,7 @@ public:
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};
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ConvergingVLIWScheduler():
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DAG(0), SchedModel(0), TRI(0), Top(TopQID, "TopQ"), Bot(BotQID, "BotQ") {}
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DAG(0), SchedModel(0), Top(TopQID, "TopQ"), Bot(BotQID, "BotQ") {}
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virtual void initialize(ScheduleDAGMI *dag);
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@ -38,11 +38,9 @@
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using namespace llvm;
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HexagonRegisterInfo::HexagonRegisterInfo(HexagonSubtarget &st,
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const HexagonInstrInfo &tii)
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HexagonRegisterInfo::HexagonRegisterInfo(HexagonSubtarget &st)
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: HexagonGenRegisterInfo(Hexagon::R31),
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Subtarget(st),
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TII(tii) {
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Subtarget(st) {
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}
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const uint16_t* HexagonRegisterInfo::getCalleeSavedRegs(const MachineFunction
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@ -130,6 +128,8 @@ void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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// Addressable stack objects are accessed using neg. offsets from %fp.
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MachineFunction &MF = *MI.getParent()->getParent();
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const HexagonInstrInfo &TII =
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*static_cast<const HexagonInstrInfo*>(MF.getTarget().getInstrInfo());
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int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
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MachineFrameInfo &MFI = *MF.getFrameInfo();
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@ -44,9 +44,8 @@ class Type;
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struct HexagonRegisterInfo : public HexagonGenRegisterInfo {
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HexagonSubtarget &Subtarget;
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const HexagonInstrInfo &TII;
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HexagonRegisterInfo(HexagonSubtarget &st, const HexagonInstrInfo &tii);
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HexagonRegisterInfo(HexagonSubtarget &st);
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/// Code Generation virtual methods...
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const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
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