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factor some BuildMI calls, no functionality change.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57544 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2008-10-15 03:47:17 +00:00
parent 26367472a2
commit 54aebde0be
1 changed files with 56 additions and 46 deletions
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102
lib/Target/X86/X86FastISel.cpp
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@ -545,6 +545,8 @@ bool X86FastISel::X86SelectCmp(Instruction *I) {
unsigned Opc = X86ChooseCmpOpcode(VT); unsigned Opc = X86ChooseCmpOpcode(VT);
unsigned ResultReg = createResultReg(&X86::GR8RegClass); unsigned ResultReg = createResultReg(&X86::GR8RegClass);
unsigned SetCCOpc;
switch (CI->getPredicate()) { switch (CI->getPredicate()) {
case CmpInst::FCMP_OEQ: { case CmpInst::FCMP_OEQ: {
unsigned EReg = createResultReg(&X86::GR8RegClass); unsigned EReg = createResultReg(&X86::GR8RegClass);
@ -553,7 +555,8 @@ bool X86FastISel::X86SelectCmp(Instruction *I) {
BuildMI(MBB, TII.get(X86::SETEr), EReg); BuildMI(MBB, TII.get(X86::SETEr), EReg);
BuildMI(MBB, TII.get(X86::SETNPr), NPReg); BuildMI(MBB, TII.get(X86::SETNPr), NPReg);
BuildMI(MBB, TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg); BuildMI(MBB, TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg);
break; UpdateValueMap(I, ResultReg);
return true;
} }
case CmpInst::FCMP_UNE: { case CmpInst::FCMP_UNE: {
unsigned NEReg = createResultReg(&X86::GR8RegClass); unsigned NEReg = createResultReg(&X86::GR8RegClass);
@ -562,100 +565,104 @@ bool X86FastISel::X86SelectCmp(Instruction *I) {
BuildMI(MBB, TII.get(X86::SETNEr), NEReg); BuildMI(MBB, TII.get(X86::SETNEr), NEReg);
BuildMI(MBB, TII.get(X86::SETPr), PReg); BuildMI(MBB, TII.get(X86::SETPr), PReg);
BuildMI(MBB, TII.get(X86::OR8rr), ResultReg).addReg(PReg).addReg(NEReg); BuildMI(MBB, TII.get(X86::OR8rr), ResultReg).addReg(PReg).addReg(NEReg);
break; UpdateValueMap(I, ResultReg);
return true;
} }
case CmpInst::FCMP_OGT: case CmpInst::FCMP_OGT:
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
BuildMI(MBB, TII.get(X86::SETAr), ResultReg); SetCCOpc = X86::SETAr;
break; break;
case CmpInst::FCMP_OGE: case CmpInst::FCMP_OGE:
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
BuildMI(MBB, TII.get(X86::SETAEr), ResultReg); SetCCOpc = X86::SETAEr;
break; break;
case CmpInst::FCMP_OLT: case CmpInst::FCMP_OLT:
BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg);
BuildMI(MBB, TII.get(X86::SETAr), ResultReg); SetCCOpc = X86::SETAr;
break; break;
case CmpInst::FCMP_OLE: case CmpInst::FCMP_OLE:
BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg);
BuildMI(MBB, TII.get(X86::SETAEr), ResultReg); SetCCOpc = X86::SETAEr;
break; break;
case CmpInst::FCMP_ONE: case CmpInst::FCMP_ONE:
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
BuildMI(MBB, TII.get(X86::SETNEr), ResultReg); SetCCOpc = X86::SETNEr;
break; break;
case CmpInst::FCMP_ORD: case CmpInst::FCMP_ORD:
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
BuildMI(MBB, TII.get(X86::SETNPr), ResultReg); SetCCOpc = X86::SETNPr;
break; break;
case CmpInst::FCMP_UNO: case CmpInst::FCMP_UNO:
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
BuildMI(MBB, TII.get(X86::SETPr), ResultReg); SetCCOpc = X86::SETPr;
break; break;
case CmpInst::FCMP_UEQ: case CmpInst::FCMP_UEQ:
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
BuildMI(MBB, TII.get(X86::SETEr), ResultReg); SetCCOpc = X86::SETEr;
break; break;
case CmpInst::FCMP_UGT: case CmpInst::FCMP_UGT:
BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg);
BuildMI(MBB, TII.get(X86::SETBr), ResultReg); SetCCOpc = X86::SETBr;
break; break;
case CmpInst::FCMP_UGE: case CmpInst::FCMP_UGE:
BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg);
BuildMI(MBB, TII.get(X86::SETBEr), ResultReg); SetCCOpc = X86::SETBEr;
break; break;
case CmpInst::FCMP_ULT: case CmpInst::FCMP_ULT:
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
BuildMI(MBB, TII.get(X86::SETBr), ResultReg); SetCCOpc = X86::SETBr;
break; break;
case CmpInst::FCMP_ULE: case CmpInst::FCMP_ULE:
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
BuildMI(MBB, TII.get(X86::SETBEr), ResultReg); SetCCOpc = X86::SETBEr;
break; break;
case CmpInst::ICMP_EQ: case CmpInst::ICMP_EQ:
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
BuildMI(MBB, TII.get(X86::SETEr), ResultReg); SetCCOpc = X86::SETEr;
break; break;
case CmpInst::ICMP_NE: case CmpInst::ICMP_NE:
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
BuildMI(MBB, TII.get(X86::SETNEr), ResultReg); SetCCOpc = X86::SETNEr;
break; break;
case CmpInst::ICMP_UGT: case CmpInst::ICMP_UGT:
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
BuildMI(MBB, TII.get(X86::SETAr), ResultReg); SetCCOpc = X86::SETAr;
break; break;
case CmpInst::ICMP_UGE: case CmpInst::ICMP_UGE:
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
BuildMI(MBB, TII.get(X86::SETAEr), ResultReg); SetCCOpc = X86::SETAEr;
break; break;
case CmpInst::ICMP_ULT: case CmpInst::ICMP_ULT:
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
BuildMI(MBB, TII.get(X86::SETBr), ResultReg); SetCCOpc = X86::SETBr;
break; break;
case CmpInst::ICMP_ULE: case CmpInst::ICMP_ULE:
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
BuildMI(MBB, TII.get(X86::SETBEr), ResultReg); SetCCOpc = X86::SETBEr;
break; break;
case CmpInst::ICMP_SGT: case CmpInst::ICMP_SGT:
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
BuildMI(MBB, TII.get(X86::SETGr), ResultReg); SetCCOpc = X86::SETGr;
break; break;
case CmpInst::ICMP_SGE: case CmpInst::ICMP_SGE:
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
BuildMI(MBB, TII.get(X86::SETGEr), ResultReg); SetCCOpc = X86::SETGEr;
break; break;
case CmpInst::ICMP_SLT: case CmpInst::ICMP_SLT:
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
BuildMI(MBB, TII.get(X86::SETLr), ResultReg); SetCCOpc = X86::SETLr;
break; break;
case CmpInst::ICMP_SLE: case CmpInst::ICMP_SLE:
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
BuildMI(MBB, TII.get(X86::SETLEr), ResultReg); SetCCOpc = X86::SETLEr;
break; break;
default: default:
return false; return false;
} }
if (SetCCOpc)
BuildMI(MBB, TII.get(SetCCOpc), ResultReg);
UpdateValueMap(I, ResultReg); UpdateValueMap(I, ResultReg);
return true; return true;
} }
@ -700,98 +707,101 @@ bool X86FastISel::X86SelectBranch(Instruction *I) {
unsigned Op1Reg = getRegForValue(CI->getOperand(1)); unsigned Op1Reg = getRegForValue(CI->getOperand(1));
if (Op1Reg == 0) return false; if (Op1Reg == 0) return false;
unsigned BranchOpc;
switch (Predicate) { switch (Predicate) {
case CmpInst::FCMP_OGT: case CmpInst::FCMP_OGT:
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
BuildMI(MBB, TII.get(X86::JA)).addMBB(TrueMBB); BranchOpc = X86::JA;
break; break;
case CmpInst::FCMP_OGE: case CmpInst::FCMP_OGE:
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
BuildMI(MBB, TII.get(X86::JAE)).addMBB(TrueMBB); BranchOpc = X86::JAE;
break; break;
case CmpInst::FCMP_OLT: case CmpInst::FCMP_OLT:
BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg);
BuildMI(MBB, TII.get(X86::JA)).addMBB(TrueMBB); BranchOpc = X86::JA;
break; break;
case CmpInst::FCMP_OLE: case CmpInst::FCMP_OLE:
BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg);
BuildMI(MBB, TII.get(X86::JAE)).addMBB(TrueMBB); BranchOpc = X86::JAE;
break; break;
case CmpInst::FCMP_ONE: case CmpInst::FCMP_ONE:
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
BuildMI(MBB, TII.get(X86::JNE)).addMBB(TrueMBB); BranchOpc = X86::JNE;
break; break;
case CmpInst::FCMP_ORD: case CmpInst::FCMP_ORD:
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
BuildMI(MBB, TII.get(X86::JNP)).addMBB(TrueMBB); BranchOpc = X86::JNP;
break; break;
case CmpInst::FCMP_UNO: case CmpInst::FCMP_UNO:
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
BuildMI(MBB, TII.get(X86::JP)).addMBB(TrueMBB); BranchOpc = X86::JP;
break; break;
case CmpInst::FCMP_UEQ: case CmpInst::FCMP_UEQ:
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
BuildMI(MBB, TII.get(X86::JE)).addMBB(TrueMBB); BranchOpc = X86::JE;
break; break;
case CmpInst::FCMP_UGT: case CmpInst::FCMP_UGT:
BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg);
BuildMI(MBB, TII.get(X86::JB)).addMBB(TrueMBB); BranchOpc = X86::JB;
break; break;
case CmpInst::FCMP_UGE: case CmpInst::FCMP_UGE:
BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg);
BuildMI(MBB, TII.get(X86::JBE)).addMBB(TrueMBB); BranchOpc = X86::JBE;
break; break;
case CmpInst::FCMP_ULT: case CmpInst::FCMP_ULT:
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
BuildMI(MBB, TII.get(X86::JB)).addMBB(TrueMBB); BranchOpc = X86::JB;
break; break;
case CmpInst::FCMP_ULE: case CmpInst::FCMP_ULE:
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
BuildMI(MBB, TII.get(X86::JBE)).addMBB(TrueMBB); BranchOpc = X86::JBE;
break; break;
case CmpInst::ICMP_EQ: case CmpInst::ICMP_EQ:
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
BuildMI(MBB, TII.get(X86::JE)).addMBB(TrueMBB); BranchOpc = X86::JE;
break; break;
case CmpInst::ICMP_NE: case CmpInst::ICMP_NE:
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
BuildMI(MBB, TII.get(X86::JNE)).addMBB(TrueMBB); BranchOpc = X86::JNE;
break; break;
case CmpInst::ICMP_UGT: case CmpInst::ICMP_UGT:
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
BuildMI(MBB, TII.get(X86::JA)).addMBB(TrueMBB); BranchOpc = X86::JA;
break; break;
case CmpInst::ICMP_UGE: case CmpInst::ICMP_UGE:
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
BuildMI(MBB, TII.get(X86::JAE)).addMBB(TrueMBB); BranchOpc = X86::JAE;
break; break;
case CmpInst::ICMP_ULT: case CmpInst::ICMP_ULT:
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
BuildMI(MBB, TII.get(X86::JB)).addMBB(TrueMBB); BranchOpc = X86::JB;
break; break;
case CmpInst::ICMP_ULE: case CmpInst::ICMP_ULE:
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
BuildMI(MBB, TII.get(X86::JBE)).addMBB(TrueMBB); BranchOpc = X86::JBE;
break; break;
case CmpInst::ICMP_SGT: case CmpInst::ICMP_SGT:
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
BuildMI(MBB, TII.get(X86::JG)).addMBB(TrueMBB); BranchOpc = X86::JG;
break; break;
case CmpInst::ICMP_SGE: case CmpInst::ICMP_SGE:
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
BuildMI(MBB, TII.get(X86::JGE)).addMBB(TrueMBB); BranchOpc = X86::JGE;
break; break;
case CmpInst::ICMP_SLT: case CmpInst::ICMP_SLT:
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
BuildMI(MBB, TII.get(X86::JL)).addMBB(TrueMBB); BranchOpc = X86::JL;
break; break;
case CmpInst::ICMP_SLE: case CmpInst::ICMP_SLE:
BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg); BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
BuildMI(MBB, TII.get(X86::JLE)).addMBB(TrueMBB); BranchOpc = X86::JLE;
break; break;
default: default:
return false; return false;
} }
BuildMI(MBB, TII.get(BranchOpc)).addMBB(TrueMBB);
FastEmitBranch(FalseMBB); FastEmitBranch(FalseMBB);
MBB->addSuccessor(TrueMBB); MBB->addSuccessor(TrueMBB);
return true; return true;