mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-23 17:29:19 +00:00
[TargetLowering] StringRefize asm constraint getters.
There is some functional change here because it changes target code from atoi(3) to StringRef::getAsInteger which has error checking. For valid constraints there should be no difference. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241411 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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@ -2679,7 +2679,7 @@ public:
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SelectionDAG *DAG = nullptr) const;
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/// Given a constraint, return the type of constraint it is for this target.
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virtual ConstraintType getConstraintType(const std::string &Constraint) const;
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virtual ConstraintType getConstraintType(StringRef Constraint) const;
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/// Given a physical register constraint (e.g. {edx}), return the register
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/// number and the register class for the register.
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@ -2692,10 +2692,9 @@ public:
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/// returns a register number of 0 and a null register class pointer.
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virtual std::pair<unsigned, const TargetRegisterClass *>
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getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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const std::string &Constraint, MVT VT) const;
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StringRef Constraint, MVT VT) const;
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virtual unsigned
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getInlineAsmMemConstraint(const std::string &ConstraintCode) const {
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virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
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if (ConstraintCode == "i")
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return InlineAsm::Constraint_i;
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else if (ConstraintCode == "m")
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@ -2105,9 +2105,8 @@ PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
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// Inline Assembler Implementation Methods
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//===----------------------------------------------------------------------===//
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TargetLowering::ConstraintType
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TargetLowering::getConstraintType(const std::string &Constraint) const {
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TargetLowering::getConstraintType(StringRef Constraint) const {
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unsigned S = Constraint.size();
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if (S == 1) {
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@ -2140,7 +2139,7 @@ TargetLowering::getConstraintType(const std::string &Constraint) const {
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}
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if (S > 1 && Constraint[0] == '{' && Constraint[S-1] == '}') {
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if (S == 8 && !Constraint.compare(1, 6, "memory", 6)) // "{memory}"
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if (S == 8 && Constraint.substr(1, 6) == "memory") // "{memory}"
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return C_Memory;
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return C_Register;
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}
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@ -2227,7 +2226,7 @@ void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
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std::pair<unsigned, const TargetRegisterClass *>
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TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *RI,
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const std::string &Constraint,
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StringRef Constraint,
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MVT VT) const {
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if (Constraint.empty() || Constraint[0] != '{')
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return std::make_pair(0u, static_cast<TargetRegisterClass*>(nullptr));
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@ -4232,7 +4232,7 @@ bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
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/// getConstraintType - Given a constraint letter, return the type of
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/// constraint it is for this target.
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AArch64TargetLowering::ConstraintType
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AArch64TargetLowering::getConstraintType(const std::string &Constraint) const {
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AArch64TargetLowering::getConstraintType(StringRef Constraint) const {
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if (Constraint.size() == 1) {
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switch (Constraint[0]) {
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default:
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@ -4283,8 +4283,7 @@ AArch64TargetLowering::getSingleConstraintMatchWeight(
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std::pair<unsigned, const TargetRegisterClass *>
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AArch64TargetLowering::getRegForInlineAsmConstraint(
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const TargetRegisterInfo *TRI, const std::string &Constraint,
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MVT VT) const {
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const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
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if (Constraint.size() == 1) {
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switch (Constraint[0]) {
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case 'r':
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@ -4320,10 +4319,9 @@ AArch64TargetLowering::getRegForInlineAsmConstraint(
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unsigned Size = Constraint.size();
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if ((Size == 4 || Size == 5) && Constraint[0] == '{' &&
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tolower(Constraint[1]) == 'v' && Constraint[Size - 1] == '}') {
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const std::string Reg =
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std::string(&Constraint[2], &Constraint[Size - 1]);
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int RegNo = atoi(Reg.c_str());
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if (RegNo >= 0 && RegNo <= 31) {
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int RegNo;
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bool Failed = Constraint.slice(2, Size - 1).getAsInteger(10, RegNo);
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if (!Failed && RegNo >= 0 && RegNo <= 31) {
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// v0 - v31 are aliases of q0 - q31.
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// By default we'll emit v0-v31 for this unless there's a modifier where
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// we'll emit the correct register as well.
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@ -471,8 +471,7 @@ private:
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std::vector<SDNode *> *Created) const override;
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bool combineRepeatedFPDivisors(unsigned NumUsers) const override;
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ConstraintType
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getConstraintType(const std::string &Constraint) const override;
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ConstraintType getConstraintType(StringRef Constraint) const override;
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unsigned getRegisterByName(const char* RegName, EVT VT) const override;
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/// Examine constraint string and operand type and determine a weight value.
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@ -483,14 +482,12 @@ private:
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std::pair<unsigned, const TargetRegisterClass *>
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getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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const std::string &Constraint,
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MVT VT) const override;
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StringRef Constraint, MVT VT) const override;
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void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
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std::vector<SDValue> &Ops,
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SelectionDAG &DAG) const override;
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unsigned getInlineAsmMemConstraint(
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const std::string &ConstraintCode) const override {
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unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
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if (ConstraintCode == "Q")
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return InlineAsm::Constraint_Q;
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// FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are
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@ -2212,9 +2212,8 @@ SDValue SITargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
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std::pair<unsigned, const TargetRegisterClass *>
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SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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const std::string &Constraint_,
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StringRef Constraint,
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MVT VT) const {
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StringRef Constraint(Constraint_);
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if (Constraint == "r") {
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switch(VT.SimpleTy) {
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default: llvm_unreachable("Unhandled type for 'r' inline asm constraint");
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@ -114,9 +114,9 @@ public:
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SDLoc DL,
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SDValue Ptr) const;
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std::pair<unsigned, const TargetRegisterClass *> getRegForInlineAsmConstraint(
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const TargetRegisterInfo *TRI,
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const std::string &Constraint, MVT VT) const override;
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std::pair<unsigned, const TargetRegisterClass *>
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getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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StringRef Constraint, MVT VT) const override;
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SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, SDLoc DL, SDValue V) const;
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};
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@ -10664,7 +10664,7 @@ bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const {
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/// getConstraintType - Given a constraint letter, return the type of
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/// constraint it is for this target.
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ARMTargetLowering::ConstraintType
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ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
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ARMTargetLowering::getConstraintType(StringRef Constraint) const {
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if (Constraint.size() == 1) {
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switch (Constraint[0]) {
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default: break;
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@ -10723,10 +10723,8 @@ ARMTargetLowering::getSingleConstraintMatchWeight(
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}
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typedef std::pair<unsigned, const TargetRegisterClass*> RCPair;
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RCPair
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ARMTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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const std::string &Constraint,
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MVT VT) const {
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RCPair ARMTargetLowering::getRegForInlineAsmConstraint(
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const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
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if (Constraint.size() == 1) {
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// GCC ARM Constraint Letters
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switch (Constraint[0]) {
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@ -324,8 +324,7 @@ namespace llvm {
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bool ExpandInlineAsm(CallInst *CI) const override;
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ConstraintType
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getConstraintType(const std::string &Constraint) const override;
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ConstraintType getConstraintType(StringRef Constraint) const override;
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/// Examine constraint string and operand type and determine a weight value.
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/// The operand object must already have been set up with the operand type.
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@ -334,8 +333,7 @@ namespace llvm {
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std::pair<unsigned, const TargetRegisterClass *>
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getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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const std::string &Constraint,
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MVT VT) const override;
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StringRef Constraint, MVT VT) const override;
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/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
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/// vector. If it is invalid, don't add anything to Ops. If hasMemory is
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@ -345,8 +343,8 @@ namespace llvm {
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std::vector<SDValue> &Ops,
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SelectionDAG &DAG) const override;
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unsigned getInlineAsmMemConstraint(
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const std::string &ConstraintCode) const override {
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unsigned
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getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
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if (ConstraintCode == "Q")
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return InlineAsm::Constraint_Q;
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else if (ConstraintCode.size() == 2) {
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@ -2338,8 +2338,7 @@ HexagonTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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std::pair<unsigned, const TargetRegisterClass *>
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HexagonTargetLowering::getRegForInlineAsmConstraint(
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const TargetRegisterInfo *TRI, const std::string &Constraint,
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MVT VT) const {
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const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
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if (Constraint.size() == 1) {
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switch (Constraint[0]) {
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case 'r': // R0-R31
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@ -179,11 +179,10 @@ bool isPositiveHalfWord(SDNode *N);
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std::pair<unsigned, const TargetRegisterClass *>
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getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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const std::string &Constraint,
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MVT VT) const override;
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StringRef Constraint, MVT VT) const override;
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unsigned getInlineAsmMemConstraint(
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const std::string &ConstraintCode) const override {
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unsigned
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getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
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if (ConstraintCode == "o")
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return InlineAsm::Constraint_o;
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else if (ConstraintCode == "v")
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@ -213,7 +213,7 @@ SDValue MSP430TargetLowering::LowerOperation(SDValue Op,
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/// getConstraintType - Given a constraint letter, return the type of
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/// constraint it is for this target.
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TargetLowering::ConstraintType
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MSP430TargetLowering::getConstraintType(const std::string &Constraint) const {
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MSP430TargetLowering::getConstraintType(StringRef Constraint) const {
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if (Constraint.size() == 1) {
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switch (Constraint[0]) {
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case 'r':
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@ -227,8 +227,7 @@ MSP430TargetLowering::getConstraintType(const std::string &Constraint) const {
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std::pair<unsigned, const TargetRegisterClass *>
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MSP430TargetLowering::getRegForInlineAsmConstraint(
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const TargetRegisterInfo *TRI, const std::string &Constraint,
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MVT VT) const {
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const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
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if (Constraint.size() == 1) {
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// GCC Constraint Letters
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switch (Constraint[0]) {
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@ -96,11 +96,10 @@ namespace llvm {
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SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
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TargetLowering::ConstraintType
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getConstraintType(const std::string &Constraint) const override;
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getConstraintType(StringRef Constraint) const override;
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std::pair<unsigned, const TargetRegisterClass *>
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getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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const std::string &Constraint,
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MVT VT) const override;
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StringRef Constraint, MVT VT) const override;
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/// isTruncateFree - Return true if it's free to truncate a value of type
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/// Ty1 to type Ty2. e.g. On msp430 it's free to truncate a i16 value in
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@ -3198,9 +3198,8 @@ MipsTargetLowering::LowerReturn(SDValue Chain,
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/// getConstraintType - Given a constraint letter, return the type of
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/// constraint it is for this target.
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MipsTargetLowering::ConstraintType MipsTargetLowering::
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getConstraintType(const std::string &Constraint) const
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{
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MipsTargetLowering::ConstraintType
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MipsTargetLowering::getConstraintType(StringRef Constraint) const {
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// Mips specific constraints
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// GCC config/mips/constraints.md
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//
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@ -3290,8 +3289,7 @@ MipsTargetLowering::getSingleConstraintMatchWeight(
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/// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag
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/// that is returned indicates whether parsing was successful. The second flag
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/// is true if the numeric part exists.
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static std::pair<bool, bool>
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parsePhysicalReg(StringRef C, std::string &Prefix,
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static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix,
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unsigned long long &Reg) {
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if (C.front() != '{' || C.back() != '}')
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return std::make_pair(false, false);
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@ -3300,7 +3298,7 @@ parsePhysicalReg(StringRef C, std::string &Prefix,
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StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1;
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I = std::find_if(B, E, std::ptr_fun(isdigit));
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Prefix.assign(B, I - B);
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Prefix = StringRef(B, I - B);
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// The second flag is set to false if no numeric characters were found.
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if (I == E)
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@ -3316,7 +3314,7 @@ parseRegForInlineAsmConstraint(StringRef C, MVT VT) const {
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const TargetRegisterInfo *TRI =
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Subtarget.getRegisterInfo();
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const TargetRegisterClass *RC;
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std::string Prefix;
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StringRef Prefix;
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unsigned long long Reg;
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std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg);
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@ -3332,7 +3330,7 @@ parseRegForInlineAsmConstraint(StringRef C, MVT VT) const {
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RC = TRI->getRegClass(Prefix == "hi" ?
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Mips::HI32RegClassID : Mips::LO32RegClassID);
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return std::make_pair(*(RC->begin()), RC);
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} else if (Prefix.compare(0, 4, "$msa") == 0) {
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} else if (Prefix.startswith("$msa")) {
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// Parse $msa(ir|csr|access|save|modify|request|map|unmap)
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// No numeric characters follow the name.
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@ -3390,7 +3388,7 @@ parseRegForInlineAsmConstraint(StringRef C, MVT VT) const {
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/// pointer.
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std::pair<unsigned, const TargetRegisterClass *>
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MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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const std::string &Constraint,
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StringRef Constraint,
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MVT VT) const {
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if (Constraint.size() == 1) {
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switch (Constraint[0]) {
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@ -478,8 +478,7 @@ namespace llvm {
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bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
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// Inline asm support
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ConstraintType
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getConstraintType(const std::string &Constraint) const override;
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ConstraintType getConstraintType(StringRef Constraint) const override;
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/// Examine constraint string and operand type and determine a weight value.
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/// The operand object must already have been set up with the operand type.
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@ -493,8 +492,7 @@ namespace llvm {
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std::pair<unsigned, const TargetRegisterClass *>
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getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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const std::string &Constraint,
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MVT VT) const override;
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StringRef Constraint, MVT VT) const override;
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/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
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/// vector. If it is invalid, don't add anything to Ops. If hasMemory is
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@ -505,8 +503,8 @@ namespace llvm {
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std::vector<SDValue> &Ops,
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SelectionDAG &DAG) const override;
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unsigned getInlineAsmMemConstraint(
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const std::string &ConstraintCode) const override {
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unsigned
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getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
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if (ConstraintCode == "R")
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return InlineAsm::Constraint_R;
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else if (ConstraintCode == "ZC")
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@ -3772,7 +3772,7 @@ bool NVPTXTargetLowering::isLegalAddressingMode(const AddrMode &AM,
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/// getConstraintType - Given a constraint letter, return the type of
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/// constraint it is for this target.
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NVPTXTargetLowering::ConstraintType
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NVPTXTargetLowering::getConstraintType(const std::string &Constraint) const {
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NVPTXTargetLowering::getConstraintType(StringRef Constraint) const {
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if (Constraint.size() == 1) {
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switch (Constraint[0]) {
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default:
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@ -3794,7 +3794,7 @@ NVPTXTargetLowering::getConstraintType(const std::string &Constraint) const {
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std::pair<unsigned, const TargetRegisterClass *>
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NVPTXTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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const std::string &Constraint,
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StringRef Constraint,
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MVT VT) const {
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if (Constraint.size() == 1) {
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switch (Constraint[0]) {
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return MVT::i1;
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}
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ConstraintType
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getConstraintType(const std::string &Constraint) const override;
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ConstraintType getConstraintType(StringRef Constraint) const override;
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std::pair<unsigned, const TargetRegisterClass *>
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getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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const std::string &Constraint,
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MVT VT) const override;
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StringRef Constraint, MVT VT) const override;
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SDValue LowerFormalArguments(
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SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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@ -10691,7 +10691,7 @@ unsigned PPCTargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
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/// getConstraintType - Given a constraint, return the type of
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/// constraint it is for this target.
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PPCTargetLowering::ConstraintType
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PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
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PPCTargetLowering::getConstraintType(StringRef Constraint) const {
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if (Constraint.size() == 1) {
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switch (Constraint[0]) {
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default: break;
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@ -10776,7 +10776,7 @@ PPCTargetLowering::getSingleConstraintMatchWeight(
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std::pair<unsigned, const TargetRegisterClass *>
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PPCTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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const std::string &Constraint,
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StringRef Constraint,
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MVT VT) const {
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if (Constraint.size() == 1) {
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// GCC RS6000 Constraint Letters
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@ -519,8 +519,7 @@ namespace llvm {
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MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
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MachineBasicBlock *MBB) const;
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ConstraintType
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getConstraintType(const std::string &Constraint) const override;
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ConstraintType getConstraintType(StringRef Constraint) const override;
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/// Examine constraint string and operand type and determine a weight value.
|
||||
/// The operand object must already have been set up with the operand type.
|
||||
@ -529,8 +528,7 @@ namespace llvm {
|
||||
|
||||
std::pair<unsigned, const TargetRegisterClass *>
|
||||
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
|
||||
const std::string &Constraint,
|
||||
MVT VT) const override;
|
||||
StringRef Constraint, MVT VT) const override;
|
||||
|
||||
/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
|
||||
/// function arguments in the caller parameter area. This is the actual
|
||||
@ -544,8 +542,8 @@ namespace llvm {
|
||||
std::vector<SDValue> &Ops,
|
||||
SelectionDAG &DAG) const override;
|
||||
|
||||
unsigned getInlineAsmMemConstraint(
|
||||
const std::string &ConstraintCode) const override {
|
||||
unsigned
|
||||
getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
|
||||
if (ConstraintCode == "es")
|
||||
return InlineAsm::Constraint_es;
|
||||
else if (ConstraintCode == "o")
|
||||
|
@ -3065,7 +3065,7 @@ SparcTargetLowering::expandAtomicRMW(MachineInstr *MI,
|
||||
/// getConstraintType - Given a constraint letter, return the type of
|
||||
/// constraint it is for this target.
|
||||
SparcTargetLowering::ConstraintType
|
||||
SparcTargetLowering::getConstraintType(const std::string &Constraint) const {
|
||||
SparcTargetLowering::getConstraintType(StringRef Constraint) const {
|
||||
if (Constraint.size() == 1) {
|
||||
switch (Constraint[0]) {
|
||||
default: break;
|
||||
@ -3139,7 +3139,7 @@ LowerAsmOperandForConstraint(SDValue Op,
|
||||
|
||||
std::pair<unsigned, const TargetRegisterClass *>
|
||||
SparcTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
|
||||
const std::string &Constraint,
|
||||
StringRef Constraint,
|
||||
MVT VT) const {
|
||||
if (Constraint.size() == 1) {
|
||||
switch (Constraint[0]) {
|
||||
|
@ -72,7 +72,7 @@ namespace llvm {
|
||||
|
||||
const char *getTargetNodeName(unsigned Opcode) const override;
|
||||
|
||||
ConstraintType getConstraintType(const std::string &Constraint) const override;
|
||||
ConstraintType getConstraintType(StringRef Constraint) const override;
|
||||
ConstraintWeight
|
||||
getSingleConstraintMatchWeight(AsmOperandInfo &info,
|
||||
const char *constraint) const override;
|
||||
@ -82,8 +82,7 @@ namespace llvm {
|
||||
SelectionDAG &DAG) const override;
|
||||
std::pair<unsigned, const TargetRegisterClass *>
|
||||
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
|
||||
const std::string &Constraint,
|
||||
MVT VT) const override;
|
||||
StringRef Constraint, MVT VT) const override;
|
||||
|
||||
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
|
||||
MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; }
|
||||
|
@ -544,7 +544,7 @@ bool SystemZTargetLowering::isTruncateFree(EVT FromVT, EVT ToVT) const {
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
TargetLowering::ConstraintType
|
||||
SystemZTargetLowering::getConstraintType(const std::string &Constraint) const {
|
||||
SystemZTargetLowering::getConstraintType(StringRef Constraint) const {
|
||||
if (Constraint.size() == 1) {
|
||||
switch (Constraint[0]) {
|
||||
case 'a': // Address register
|
||||
@ -641,13 +641,14 @@ getSingleConstraintMatchWeight(AsmOperandInfo &info,
|
||||
// has already been verified. MC is the class associated with "t" and
|
||||
// Map maps 0-based register numbers to LLVM register numbers.
|
||||
static std::pair<unsigned, const TargetRegisterClass *>
|
||||
parseRegisterNumber(const std::string &Constraint,
|
||||
const TargetRegisterClass *RC, const unsigned *Map) {
|
||||
parseRegisterNumber(StringRef Constraint, const TargetRegisterClass *RC,
|
||||
const unsigned *Map) {
|
||||
assert(*(Constraint.end()-1) == '}' && "Missing '}'");
|
||||
if (isdigit(Constraint[2])) {
|
||||
std::string Suffix(Constraint.data() + 2, Constraint.size() - 2);
|
||||
unsigned Index = atoi(Suffix.c_str());
|
||||
if (Index < 16 && Map[Index])
|
||||
unsigned Index;
|
||||
bool Failed =
|
||||
Constraint.slice(2, Constraint.size() - 1).getAsInteger(10, Index);
|
||||
if (!Failed && Index < 16 && Map[Index])
|
||||
return std::make_pair(Map[Index], RC);
|
||||
}
|
||||
return std::make_pair(0U, nullptr);
|
||||
@ -655,8 +656,7 @@ parseRegisterNumber(const std::string &Constraint,
|
||||
|
||||
std::pair<unsigned, const TargetRegisterClass *>
|
||||
SystemZTargetLowering::getRegForInlineAsmConstraint(
|
||||
const TargetRegisterInfo *TRI, const std::string &Constraint,
|
||||
MVT VT) const {
|
||||
const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
|
||||
if (Constraint.size() == 1) {
|
||||
// GCC Constraint Letters
|
||||
switch (Constraint[0]) {
|
||||
@ -687,7 +687,7 @@ SystemZTargetLowering::getRegForInlineAsmConstraint(
|
||||
return std::make_pair(0U, &SystemZ::FP32BitRegClass);
|
||||
}
|
||||
}
|
||||
if (Constraint[0] == '{') {
|
||||
if (Constraint.size() > 0 && Constraint[0] == '{') {
|
||||
// We need to override the default register parsing for GPRs and FPRs
|
||||
// because the interpretation depends on VT. The internal names of
|
||||
// the registers are also different from the external names
|
||||
|
@ -379,10 +379,9 @@ public:
|
||||
const char *getTargetNodeName(unsigned Opcode) const override;
|
||||
std::pair<unsigned, const TargetRegisterClass *>
|
||||
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
|
||||
const std::string &Constraint,
|
||||
MVT VT) const override;
|
||||
StringRef Constraint, MVT VT) const override;
|
||||
TargetLowering::ConstraintType
|
||||
getConstraintType(const std::string &Constraint) const override;
|
||||
getConstraintType(StringRef Constraint) const override;
|
||||
TargetLowering::ConstraintWeight
|
||||
getSingleConstraintMatchWeight(AsmOperandInfo &info,
|
||||
const char *constraint) const override;
|
||||
@ -391,8 +390,7 @@ public:
|
||||
std::vector<SDValue> &Ops,
|
||||
SelectionDAG &DAG) const override;
|
||||
|
||||
unsigned getInlineAsmMemConstraint(
|
||||
const std::string &ConstraintCode) const override {
|
||||
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
|
||||
if (ConstraintCode.size() == 1) {
|
||||
switch(ConstraintCode[0]) {
|
||||
default:
|
||||
|
@ -25164,7 +25164,7 @@ bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
|
||||
(matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
|
||||
matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
|
||||
AsmPieces.clear();
|
||||
const std::string &ConstraintsStr = IA->getConstraintString();
|
||||
StringRef ConstraintsStr = IA->getConstraintString();
|
||||
SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
|
||||
array_pod_sort(AsmPieces.begin(), AsmPieces.end());
|
||||
if (clobbersFlagRegisters(AsmPieces))
|
||||
@ -25178,7 +25178,7 @@ bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
|
||||
matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
|
||||
matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
|
||||
AsmPieces.clear();
|
||||
const std::string &ConstraintsStr = IA->getConstraintString();
|
||||
StringRef ConstraintsStr = IA->getConstraintString();
|
||||
SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
|
||||
array_pod_sort(AsmPieces.begin(), AsmPieces.end());
|
||||
if (clobbersFlagRegisters(AsmPieces))
|
||||
@ -25205,7 +25205,7 @@ bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
|
||||
/// getConstraintType - Given a constraint letter, return the type of
|
||||
/// constraint it is for this target.
|
||||
X86TargetLowering::ConstraintType
|
||||
X86TargetLowering::getConstraintType(const std::string &Constraint) const {
|
||||
X86TargetLowering::getConstraintType(StringRef Constraint) const {
|
||||
if (Constraint.size() == 1) {
|
||||
switch (Constraint[0]) {
|
||||
case 'R':
|
||||
@ -25537,7 +25537,7 @@ void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
|
||||
|
||||
std::pair<unsigned, const TargetRegisterClass *>
|
||||
X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
|
||||
const std::string &Constraint,
|
||||
StringRef Constraint,
|
||||
MVT VT) const {
|
||||
// First, see if this is a constraint that directly corresponds to an LLVM
|
||||
// register class.
|
||||
|
@ -707,8 +707,7 @@ namespace llvm {
|
||||
|
||||
bool ExpandInlineAsm(CallInst *CI) const override;
|
||||
|
||||
ConstraintType
|
||||
getConstraintType(const std::string &Constraint) const override;
|
||||
ConstraintType getConstraintType(StringRef Constraint) const override;
|
||||
|
||||
/// Examine constraint string and operand type and determine a weight value.
|
||||
/// The operand object must already have been set up with the operand type.
|
||||
@ -726,8 +725,8 @@ namespace llvm {
|
||||
std::vector<SDValue> &Ops,
|
||||
SelectionDAG &DAG) const override;
|
||||
|
||||
unsigned getInlineAsmMemConstraint(
|
||||
const std::string &ConstraintCode) const override {
|
||||
unsigned
|
||||
getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
|
||||
if (ConstraintCode == "i")
|
||||
return InlineAsm::Constraint_i;
|
||||
else if (ConstraintCode == "o")
|
||||
@ -745,8 +744,7 @@ namespace llvm {
|
||||
/// error, this returns a register number of 0.
|
||||
std::pair<unsigned, const TargetRegisterClass *>
|
||||
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
|
||||
const std::string &Constraint,
|
||||
MVT VT) const override;
|
||||
StringRef Constraint, MVT VT) const override;
|
||||
|
||||
/// Return true if the addressing mode represented
|
||||
/// by AM is legal for this target, for a load/store of the specified type.
|
||||
|
@ -1970,7 +1970,7 @@ XCoreTargetLowering::isLegalAddressingMode(const AddrMode &AM,
|
||||
|
||||
std::pair<unsigned, const TargetRegisterClass *>
|
||||
XCoreTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
|
||||
const std::string &Constraint,
|
||||
StringRef Constraint,
|
||||
MVT VT) const {
|
||||
if (Constraint.size() == 1) {
|
||||
switch (Constraint[0]) {
|
||||
|
@ -175,8 +175,7 @@ namespace llvm {
|
||||
// Inline asm support
|
||||
std::pair<unsigned, const TargetRegisterClass *>
|
||||
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
|
||||
const std::string &Constraint,
|
||||
MVT VT) const override;
|
||||
StringRef Constraint, MVT VT) const override;
|
||||
|
||||
// Expand specifics
|
||||
SDValue TryExpandADDWithMul(SDNode *Op, SelectionDAG &DAG) const;
|
||||
|
Loading…
Reference in New Issue
Block a user