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Remove MethodProtos/MethodBodies and allocation_order_begin/end.
Targets that need to change the default allocation order should use the AltOrders mechanism instead. See the X86 and ARM targets for examples. The allocation_order_begin() and allocation_order_end() methods have been replaced with getRawAllocationOrder(), and there is further support functions in RegisterClassInfo. It is no longer possible to insert arbitrary code into generated register classes. This is a feature. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133332 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -133,12 +133,6 @@ class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
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// model instruction operand constraints, and should have isAllocatable = 0.
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bit isAllocatable = 1;
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// MethodProtos/MethodBodies - These members can be used to insert arbitrary
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// code into a generated register class. The normal usage of this is to
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// overload virtual methods.
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code MethodProtos = [{}];
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code MethodBodies = [{}];
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// AltOrders - List of alternative allocation orders. The default order is
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// MemberList itself, and that is good enough for most targets since the
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// register allocators automatically remove reserved registers and move
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@ -237,29 +237,6 @@ public:
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return SuperClasses[0] != 0;
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}
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/// allocation_order_begin/end - These methods define a range of registers
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/// which specify the registers in this class that are valid to register
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/// allocate, and the preferred order to allocate them in. For example,
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/// callee saved registers should be at the end of the list, because it is
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/// cheaper to allocate caller saved registers.
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///
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/// These methods take a MachineFunction argument, which can be used to tune
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/// the allocatable registers based on the characteristics of the function,
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/// subtarget, or other criteria.
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///
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/// Register allocators should account for the fact that an allocation
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/// order iterator may return a reserved register and always check
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/// if the register is allocatable (getAllocatableSet()) before using it.
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///
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/// By default, these methods return all registers in the class.
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///
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virtual iterator allocation_order_begin(const MachineFunction &MF) const {
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return begin();
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}
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virtual iterator allocation_order_end(const MachineFunction &MF) const {
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return end();
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}
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/// getRawAllocationOrder - Returns the preferred order for allocating
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/// registers from this register class in MF. The raw order comes directly
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/// from the .td file and may include reserved registers that are not
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@ -276,9 +253,7 @@ public:
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///
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virtual
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ArrayRef<unsigned> getRawAllocationOrder(const MachineFunction &MF) const {
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iterator B = allocation_order_begin(MF);
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iterator E = allocation_order_end(MF);
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return ArrayRef<unsigned>(B, E - B);
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return ArrayRef<unsigned>(begin(), getNumRegs());
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}
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/// getSize - Return the size of the register in bytes, which is also the size
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@ -225,8 +225,6 @@ CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
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SpillAlignment = R->getValueAsInt("Alignment");
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CopyCost = R->getValueAsInt("CopyCost");
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Allocatable = R->getValueAsBit("isAllocatable");
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MethodBodies = R->getValueAsCode("MethodBodies");
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MethodProtos = R->getValueAsCode("MethodProtos");
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AltOrderSelect = R->getValueAsCode("AltOrderSelect");
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}
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@ -97,7 +97,7 @@ namespace llvm {
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bool Allocatable;
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// Map SubRegIndex -> RegisterClass
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DenseMap<Record*,Record*> SubRegClasses;
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std::string MethodProtos, MethodBodies, AltOrderSelect;
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std::string AltOrderSelect;
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const std::string &getName() const;
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const std::vector<MVT::SimpleValueType> &getValueTypes() const {return VTs;}
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@ -117,7 +117,7 @@ void RegisterInfoEmitter::runHeader(raw_ostream &OS) {
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if (!RC.AltOrderSelect.empty())
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OS << " ArrayRef<unsigned> "
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"getRawAllocationOrder(const MachineFunction&) const;\n";
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OS << RC.MethodProtos << " };\n";
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OS << " };\n";
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// Output the extern for the instance.
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OS << " extern " << Name << "Class\t" << Name << "RegClass;\n";
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@ -356,7 +356,6 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
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// Emit methods.
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for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
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const CodeGenRegisterClass &RC = RegisterClasses[i];
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OS << RC.MethodBodies << "\n";
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OS << RC.getName() << "Class::" << RC.getName()
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<< "Class() : TargetRegisterClass("
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<< RC.getName() + "RegClassID" << ", "
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