From 54c5bc87992ebeaa9e71f2bfb60ac5cf74b77db3 Mon Sep 17 00:00:00 2001
From: Akira Hatanaka <ahatanaka@mips.com>
Date: Thu, 21 Jun 2012 20:39:10 +0000
Subject: [PATCH] 1. fix null program output after some other changes 2.
 re-enable null.ll test 3. fix some minor style violations

Patch by Reed Kotler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158935 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/Mips/Mips16InstrInfo.td    | 27 ++++++++++++++++++++-------
 lib/Target/Mips/MipsFrameLowering.cpp |  3 ++-
 lib/Target/Mips/MipsISelDAGToDAG.cpp  |  9 ++++++++-
 test/CodeGen/Mips/null.ll             |  4 ----
 4 files changed, 30 insertions(+), 13 deletions(-)

diff --git a/lib/Target/Mips/Mips16InstrInfo.td b/lib/Target/Mips/Mips16InstrInfo.td
index fc530939ed5..2e0239377d5 100644
--- a/lib/Target/Mips/Mips16InstrInfo.td
+++ b/lib/Target/Mips/Mips16InstrInfo.td
@@ -11,19 +11,29 @@
 //
 //===----------------------------------------------------------------------===//
 
+class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> {
+  let Predicates = [InMips16Mode];
+}
+
+def LI16E      : FEXT_RI16<0b01101, (outs CPU16Regs:$rx),
+                           (ins uimm16:$amt),
+                           !strconcat("li", "\t$rx, $amt"),
+                           [(set CPU16Regs:$rx, immZExt16:$amt )],IILoad>;
+
 let isReturn=1, isTerminator=1, hasDelaySlot=1, isCodeGenOnly=1,
     isBarrier=1, hasCtrlDep=1, rx=0, nd=0, l=0, ra=0  in
-def RET16 : FRR16_JALRC < (outs), (ins CPURAReg:$target),
-                   "jr\t$target", [(MipsRet CPURAReg:$target)], IIBranch>;
+def RET16 : FRR16_JALRC 
+            < (outs), (ins CPURAReg:$target),
+              "jr\t$target", [(MipsRet CPURAReg:$target)], IIBranch>;
 
 // As stack alignment is always done with addiu, we need a 16-bit immediate
 let Defs = [SP], Uses = [SP] in {
 def ADJCALLSTACKDOWN16 : MipsPseudo16<(outs), (ins uimm16:$amt),
-                                  "!ADJCALLSTACKDOWN $amt",
-                                  [(callseq_start timm:$amt)]>;
+                                      "!ADJCALLSTACKDOWN $amt",
+                                      [(callseq_start timm:$amt)]>;
 def ADJCALLSTACKUP16   : MipsPseudo16<(outs), (ins uimm16:$amt1, uimm16:$amt2),
-                                  "!ADJCALLSTACKUP $amt1",
-                                  [(callseq_end timm:$amt1, timm:$amt2)]>;
+                                      "!ADJCALLSTACKUP $amt1",
+                                      [(callseq_end timm:$amt1, timm:$amt2)]>;
 }
 
 
@@ -31,4 +41,7 @@ def ADJCALLSTACKUP16   : MipsPseudo16<(outs), (ins uimm16:$amt1, uimm16:$amt2),
 let isCall=1, hasDelaySlot=1, nd=0, l=0, ra=0 in
 def JumpLinkReg16:
     FRR16_JALRC<(outs), (ins CPU16Regs:$rs, variable_ops),
-       "jalr \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>;
+                "jalr \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>;
+
+// Small immediates
+def : Mips16Pat<(i32 immZExt16:$in), (LI16E immZExt16:$in)>;
diff --git a/lib/Target/Mips/MipsFrameLowering.cpp b/lib/Target/Mips/MipsFrameLowering.cpp
index f7baca92466..15ab1c30cec 100644
--- a/lib/Target/Mips/MipsFrameLowering.cpp
+++ b/lib/Target/Mips/MipsFrameLowering.cpp
@@ -112,7 +112,8 @@ void MipsFrameLowering::emitPrologue(MachineFunction &MF) const {
 
   // First, compute final stack size.
   unsigned StackAlign = getStackAlignment();
-  uint64_t StackSize = MFI->getObjectOffset(MipsFI->getGlobalRegFI()) +
+  uint64_t StackSize = STI.inMips16Mode()? 0:
+    MFI->getObjectOffset(MipsFI->getGlobalRegFI()) +
     StackAlign + RoundUpToAlignment(MFI->getStackSize(), StackAlign);
 
    // Update stack size
diff --git a/lib/Target/Mips/MipsISelDAGToDAG.cpp b/lib/Target/Mips/MipsISelDAGToDAG.cpp
index 4236f74dea3..15e745f7ea1 100644
--- a/lib/Target/Mips/MipsISelDAGToDAG.cpp
+++ b/lib/Target/Mips/MipsISelDAGToDAG.cpp
@@ -125,7 +125,10 @@ void MipsDAGToDAGISel::InitGlobalBaseReg(MachineFunction &MF) {
   const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
   DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
   unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
-  int FI = MipsFI->initGlobalRegFI();
+  int FI;  // should initialize this to some kind of null
+
+  if (!Subtarget.inMips16Mode())
+    FI= MipsFI->initGlobalRegFI();
 
   const TargetRegisterClass *RC = Subtarget.isABI_N64() ?
     (const TargetRegisterClass*)&Mips::CPU64RegsRegClass :
@@ -187,6 +190,10 @@ void MipsDAGToDAGISel::InitGlobalBaseReg(MachineFunction &MF) {
 
   assert(Subtarget.isABI_O32());
 
+  if (Subtarget.inMips16Mode())
+    return; // no need to load GP. It can be calculated anywhere
+
+
   // For O32 ABI, the following instruction sequence is emitted to initialize
   // the global base register:
   //
diff --git a/test/CodeGen/Mips/null.ll b/test/CodeGen/Mips/null.ll
index 3f55fa77e9c..7beae99c455 100644
--- a/test/CodeGen/Mips/null.ll
+++ b/test/CodeGen/Mips/null.ll
@@ -1,9 +1,5 @@
 ; RUN: llc  -march=mipsel -mcpu=mips16 < %s | FileCheck %s -check-prefix=16
 
-; FIXME: Disabled temporarily because it should not have worked previously
-; and will be fixed after a subsequent patch
-; REQUIRES: disabled
-
 
 define i32 @main() nounwind {
 entry: