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https://github.com/c64scene-ar/llvm-6502.git
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Add instruction encodings and disassembly for 1r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170293 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2,6 +2,7 @@ set(LLVM_TARGET_DEFINITIONS XCore.td)
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tablegen(LLVM XCoreGenRegisterInfo.inc -gen-register-info)
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tablegen(LLVM XCoreGenInstrInfo.inc -gen-instr-info)
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tablegen(LLVM XCoreGenDisassemblerTables.inc -gen-disassembler)
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tablegen(LLVM XCoreGenAsmWriter.inc -gen-asm-writer)
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tablegen(LLVM XCoreGenDAGISel.inc -gen-dag-isel)
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tablegen(LLVM XCoreGenCallingConv.inc -gen-callingconv)
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@ -10,4 +10,7 @@
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LEVEL = ../../../..
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LIBRARYNAME = LLVMXCoreDisassembler
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# Hack: we need to include 'main' XCore target directory to grab private headers
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CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
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include $(LEVEL)/Makefile.common
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@ -11,8 +11,11 @@
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//
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//===----------------------------------------------------------------------===//
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#include "XCore.h"
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#include "XCoreRegisterInfo.h"
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#include "llvm/MC/MCDisassembler.h"
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#include "llvm/MC/MCFixedLenDisassembler.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/MemoryObject.h"
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#include "llvm/Support/TargetRegistry.h"
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@ -25,11 +28,12 @@ namespace {
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/// XCoreDisassembler - a disasembler class for XCore.
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class XCoreDisassembler : public MCDisassembler {
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const MCRegisterInfo *RegInfo;
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public:
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/// Constructor - Initializes the disassembler.
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///
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XCoreDisassembler(const MCSubtargetInfo &STI) :
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MCDisassembler(STI) {}
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XCoreDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info) :
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MCDisassembler(STI), RegInfo(Info) {}
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/// getInstruction - See MCDisassembler.
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virtual DecodeStatus getInstruction(MCInst &instr,
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@ -38,8 +42,50 @@ public:
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uint64_t address,
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raw_ostream &vStream,
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raw_ostream &cStream) const;
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};
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const MCRegisterInfo *getRegInfo() const { return RegInfo; }
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};
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}
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static bool readInstruction16(const MemoryObject ®ion,
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uint64_t address,
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uint64_t &size,
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uint16_t &insn) {
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uint8_t Bytes[4];
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// We want to read exactly 2 Bytes of data.
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if (region.readBytes(address, 2, Bytes, NULL) == -1) {
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size = 0;
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return false;
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}
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// Encoded as a little-endian 16-bit word in the stream.
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insn = (Bytes[0] << 0) | (Bytes[1] << 8);
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return true;
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}
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static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
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const XCoreDisassembler *Dis = static_cast<const XCoreDisassembler*>(D);
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return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo);
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}
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static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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#include "XCoreGenDisassemblerTables.inc"
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static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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if (RegNo > 11)
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return MCDisassembler::Fail;
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unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo);
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Inst.addOperand(MCOperand::CreateReg(Reg));
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return MCDisassembler::Success;
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}
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MCDisassembler::DecodeStatus
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@ -49,6 +95,20 @@ XCoreDisassembler::getInstruction(MCInst &instr,
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uint64_t Address,
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raw_ostream &vStream,
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raw_ostream &cStream) const {
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uint16_t low;
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if (!readInstruction16(Region, Address, Size, low)) {
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return Fail;
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}
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// Calling the auto-generated decoder function.
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DecodeStatus Result = decodeInstruction(DecoderTable16, instr, low, Address,
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this, STI);
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if (Result != Fail) {
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Size = 2;
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return Result;
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}
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return Fail;
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}
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@ -58,7 +118,7 @@ namespace llvm {
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static MCDisassembler *createXCoreDisassembler(const Target &T,
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const MCSubtargetInfo &STI) {
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return new XCoreDisassembler(STI);
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return new XCoreDisassembler(STI, T.createMCRegInfo(""));
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}
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extern "C" void LLVMInitializeXCoreDisassembler() {
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@ -15,7 +15,7 @@ TARGET = XCore
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BUILT_SOURCES = XCoreGenRegisterInfo.inc XCoreGenInstrInfo.inc \
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XCoreGenAsmWriter.inc \
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XCoreGenDAGISel.inc XCoreGenCallingConv.inc \
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XCoreGenSubtargetInfo.inc
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XCoreGenDisassemblerTables.inc XCoreGenSubtargetInfo.inc
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DIRS = Disassembler InstPrinter TargetInfo MCTargetDesc
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@ -20,6 +20,7 @@ class InstXCore<int sz, dag outs, dag ins, string asmstr, list<dag> pattern>
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let AsmString = asmstr;
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let Pattern = pattern;
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let Size = sz;
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field bits<32> SoftFail = 0;
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}
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// XCore pseudo instructions format
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@ -84,8 +85,14 @@ class _FL2R<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<4, outs, ins, asmstr, pattern> {
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}
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class _F1R<dag outs, dag ins, string asmstr, list<dag> pattern>
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class _F1R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<2, outs, ins, asmstr, pattern> {
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bits<4> a;
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let Inst{15-11} = opc{5-1};
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let Inst{10-5} = 0b111111;
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let Inst{4} = opc{0};
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let Inst{3-0} = a;
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}
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class _F0R<dag outs, dag ins, string asmstr, list<dag> pattern>
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@ -946,17 +946,17 @@ def ENDIN_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
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// TODO edu, eeu, waitet, waitef, tstart, clrtp
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// setdp, setcp, setev, kcall
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// dgetreg
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def MSYNC_1r : _F1R<(outs), (ins GRRegs:$i),
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"msync res[$i]",
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[(int_xcore_msync GRRegs:$i)]>;
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def MJOIN_1r : _F1R<(outs), (ins GRRegs:$i),
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"mjoin res[$i]",
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[(int_xcore_mjoin GRRegs:$i)]>;
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def MSYNC_1r : _F1R<0b000111, (outs), (ins GRRegs:$a),
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"msync res[$a]",
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[(int_xcore_msync GRRegs:$a)]>;
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def MJOIN_1r : _F1R<0b000101, (outs), (ins GRRegs:$a),
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"mjoin res[$a]",
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[(int_xcore_mjoin GRRegs:$a)]>;
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let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
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def BAU_1r : _F1R<(outs), (ins GRRegs:$addr),
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"bau $addr",
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[(brind GRRegs:$addr)]>;
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def BAU_1r : _F1R<0b001001, (outs), (ins GRRegs:$a),
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"bau $a",
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[(brind GRRegs:$a)]>;
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let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
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def BR_JT : PseudoInstXCore<(outs), (ins InlineJT:$t, GRRegs:$i),
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@ -969,49 +969,49 @@ def BR_JT32 : PseudoInstXCore<(outs), (ins InlineJT32:$t, GRRegs:$i),
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[(XCoreBR_JT32 tjumptable:$t, GRRegs:$i)]>;
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let Defs=[SP], neverHasSideEffects=1 in
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def SETSP_1r : _F1R<(outs), (ins GRRegs:$src),
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"set sp, $src",
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def SETSP_1r : _F1R<0b001011, (outs), (ins GRRegs:$a),
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"set sp, $a",
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[]>;
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let hasCtrlDep = 1 in
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def ECALLT_1r : _F1R<(outs), (ins GRRegs:$src),
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"ecallt $src",
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def ECALLT_1r : _F1R<0b010011, (outs), (ins GRRegs:$a),
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"ecallt $a",
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[]>;
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let hasCtrlDep = 1 in
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def ECALLF_1r : _F1R<(outs), (ins GRRegs:$src),
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"ecallf $src",
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def ECALLF_1r : _F1R<0b010010, (outs), (ins GRRegs:$a),
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"ecallf $a",
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[]>;
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let isCall=1,
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// All calls clobber the link register and the non-callee-saved registers:
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Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in {
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def BLA_1r : _F1R<(outs), (ins GRRegs:$addr),
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"bla $addr",
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[(XCoreBranchLink GRRegs:$addr)]>;
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def BLA_1r : _F1R<0b001000, (outs), (ins GRRegs:$a),
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"bla $a",
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[(XCoreBranchLink GRRegs:$a)]>;
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}
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def SYNCR_1r : _F1R<(outs), (ins GRRegs:$r),
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"syncr res[$r]",
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[(int_xcore_syncr GRRegs:$r)]>;
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def SYNCR_1r : _F1R<0b100001, (outs), (ins GRRegs:$a),
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"syncr res[$a]",
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[(int_xcore_syncr GRRegs:$a)]>;
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def FREER_1r : _F1R<(outs), (ins GRRegs:$r),
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"freer res[$r]",
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[(int_xcore_freer GRRegs:$r)]>;
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def FREER_1r : _F1R<0b000100, (outs), (ins GRRegs:$a),
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"freer res[$a]",
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[(int_xcore_freer GRRegs:$a)]>;
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let Uses=[R11] in {
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def SETV_1r : _F1R<(outs), (ins GRRegs:$r),
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"setv res[$r], r11",
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[(int_xcore_setv GRRegs:$r, R11)]>;
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def SETV_1r : _F1R<0b010001, (outs), (ins GRRegs:$a),
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"setv res[$a], r11",
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[(int_xcore_setv GRRegs:$a, R11)]>;
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def SETEV_1r : _F1R<(outs), (ins GRRegs:$r),
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"setev res[$r], r11",
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[(int_xcore_setev GRRegs:$r, R11)]>;
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def SETEV_1r : _F1R<0b001111, (outs), (ins GRRegs:$a),
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"setev res[$a], r11",
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[(int_xcore_setev GRRegs:$a, R11)]>;
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}
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def EEU_1r : _F1R<(outs), (ins GRRegs:$r),
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"eeu res[$r]",
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[(int_xcore_eeu GRRegs:$r)]>;
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def EEU_1r : _F1R<0b000001, (outs), (ins GRRegs:$a),
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"eeu res[$a]",
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[(int_xcore_eeu GRRegs:$a)]>;
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// Zero operand short
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// TODO freet, ldspc, stspc, ldssr, stssr, ldsed, stsed,
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@ -45,10 +45,10 @@ def LR : Ri<15, "lr">, DwarfRegNum<[15]>;
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def GRRegs : RegisterClass<"XCore", [i32], 32,
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// Return values and arguments
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(add R0, R1, R2, R3,
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// Not preserved across procedure calls
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R11,
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// Callee save
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R4, R5, R6, R7, R8, R9, R10)>;
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R4, R5, R6, R7, R8, R9, R10,
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// Not preserved across procedure calls
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R11)>;
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// Reserved
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def RRegs : RegisterClass<"XCore", [i32], 32, (add CP, DP, SP, LR)> {
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