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When legalizing brcond ->brcc or select -> selectcc, make sure to truncate
the old condition to a one bit value. The incoming value must have been promoted, and the top bits are undefined. This causes us to generate: _test: rlwinm r2, r3, 0, 31, 31 li r3, 17 cmpwi cr0, r2, 0 bne .LBB_test_2 ; .LBB_test_1: ; li r3, 1 .LBB_test_2: ; blr instead of: _test: rlwinm r2, r3, 0, 31, 31 li r2, 17 cmpwi cr0, r3, 0 bne .LBB_test_2 ; .LBB_test_1: ; li r2, 1 .LBB_test_2: ; or r3, r2, r2 blr for: int %test(bool %c) { %retval = select bool %c, int 17, int 1 ret int %retval } git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22947 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -681,6 +681,10 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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Tmp2.getOperand(0), Tmp2.getOperand(1),
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Tmp2.getOperand(0), Tmp2.getOperand(1),
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Node->getOperand(2));
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Node->getOperand(2));
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} else {
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} else {
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// Make sure the condition is either zero or one. It may have been
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// promoted from something else.
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Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
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Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
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Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
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DAG.getCondCode(ISD::SETNE), Tmp2,
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DAG.getCondCode(ISD::SETNE), Tmp2,
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DAG.getConstant(0, Tmp2.getValueType()),
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DAG.getConstant(0, Tmp2.getValueType()),
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@ -1072,6 +1076,9 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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Tmp2, Tmp3,
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Tmp2, Tmp3,
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cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
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cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
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} else {
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} else {
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// Make sure the condition is either zero or one. It may have been
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// promoted from something else.
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Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
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Result = DAG.getSelectCC(Tmp1,
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Result = DAG.getSelectCC(Tmp1,
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DAG.getConstant(0, Tmp1.getValueType()),
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DAG.getConstant(0, Tmp1.getValueType()),
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Tmp2, Tmp3, ISD::SETNE);
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Tmp2, Tmp3, ISD::SETNE);
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