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https://github.com/c64scene-ar/llvm-6502.git
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isel (i32 anyext i16) as insert_subreg when 16-bit ops are being promoted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101979 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
fe5dcbc27d
commit
5528e7bcb1
@ -64,9 +64,6 @@ DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
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static cl::opt<bool>
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Disable16Bit("disable-16bit", cl::Hidden,
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cl::desc("Disable use of 16-bit instructions"));
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static cl::opt<bool>
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Promote16Bit("promote-16bit", cl::Hidden,
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cl::desc("Promote 16-bit instructions"));
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// Forward declarations.
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static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
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@ -6016,7 +6013,7 @@ SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
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}
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// Otherwise just emit a CMP with 0, which is the TEST pattern.
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if (Promote16Bit && Op.getValueType() == MVT::i16)
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if (Subtarget->shouldPromote16Bit() && Op.getValueType() == MVT::i16)
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Op = DAG.getNode(ISD::ANY_EXTEND, Op.getDebugLoc(), MVT::i32, Op);
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return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
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DAG.getConstant(0, Op.getValueType()));
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@ -6031,7 +6028,7 @@ SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
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return EmitTest(Op0, X86CC, DAG);
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DebugLoc dl = Op0.getDebugLoc();
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if (Promote16Bit && Op0.getValueType() == MVT::i16) {
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if (Subtarget->shouldPromote16Bit() && Op0.getValueType() == MVT::i16) {
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Op0 = DAG.getNode(ISD::ANY_EXTEND, Op0.getDebugLoc(), MVT::i32, Op0);
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Op1 = DAG.getNode(ISD::ANY_EXTEND, Op1.getDebugLoc(), MVT::i32, Op1);
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}
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@ -6040,8 +6037,8 @@ SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
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/// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
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/// if it's possible.
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static SDValue LowerToBT(SDValue And, ISD::CondCode CC,
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DebugLoc dl, SelectionDAG &DAG) {
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SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
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DebugLoc dl, SelectionDAG &DAG) const {
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SDValue Op0 = And.getOperand(0);
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SDValue Op1 = And.getOperand(1);
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if (Op0.getOpcode() == ISD::TRUNCATE)
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@ -6078,7 +6075,7 @@ static SDValue LowerToBT(SDValue And, ISD::CondCode CC,
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// the encoding for the i16 version is larger than the i32 version.
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// Also promote i16 to i32 for performance / code size reason.
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if (LHS.getValueType() == MVT::i8 ||
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(Promote16Bit && LHS.getValueType() == MVT::i16))
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(Subtarget->shouldPromote16Bit() && LHS.getValueType() == MVT::i16))
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LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
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// If the operand types disagree, extend the shift amount to match. Since
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@ -9960,7 +9957,7 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
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bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
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if (!isTypeLegal(VT))
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return false;
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if (!Promote16Bit || VT != MVT::i16)
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if (!Subtarget->shouldPromote16Bit() || VT != MVT::i16)
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return true;
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switch (Opc) {
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@ -9989,7 +9986,7 @@ bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
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/// beneficial for dag combiner to promote the specified node. If true, it
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/// should return the desired promotion type by reference.
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bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
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if (!Promote16Bit)
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if (!Subtarget->shouldPromote16Bit())
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return false;
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EVT VT = Op.getValueType();
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@ -685,6 +685,8 @@ namespace llvm {
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SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerToBT(SDValue And, ISD::CondCode CC,
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DebugLoc dl, SelectionDAG &DAG) const;
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SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
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@ -331,6 +331,8 @@ def OptForSpeed : Predicate<"!OptForSize">;
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def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
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def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
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def HasAES : Predicate<"Subtarget->hasAES()">;
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def Promote16Bit : Predicate<"Subtarget->shouldPromote16Bit()">;
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def NotPromote16Bit : Predicate<"!Subtarget->shouldPromote16Bit()">;
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//===----------------------------------------------------------------------===//
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// X86 Instruction Format Definitions.
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@ -4476,7 +4478,13 @@ def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
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// avoid partial-register updates.
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def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
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def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
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def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>;
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def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>,
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Requires<[NotPromote16Bit]>;
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def : Pat<(i32 (anyext GR16:$src)),
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(INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>,
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Requires<[Promote16Bit]>;
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//===----------------------------------------------------------------------===//
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// Some peepholes
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@ -16,6 +16,7 @@
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#include "X86InstrInfo.h"
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#include "X86GenSubtarget.inc"
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#include "llvm/GlobalValue.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/System/Host.h"
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@ -24,6 +25,10 @@
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#include "llvm/ADT/SmallVector.h"
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using namespace llvm;
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static cl::opt<bool>
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DoPromote16Bit("promote-16bit", cl::Hidden,
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cl::desc("Promote 16-bit instructions"));
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#if defined(_MSC_VER)
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#include <intrin.h>
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#endif
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@ -293,6 +298,7 @@ X86Subtarget::X86Subtarget(const std::string &TT, const std::string &FS,
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, IsBTMemSlow(false)
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, IsUAMemFast(false)
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, HasVectorUAMem(false)
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, Promote16Bit(DoPromote16Bit)
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, DarwinVers(0)
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, stackAlignment(8)
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// FIXME: this is a known good value for Yonah. How about others?
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@ -85,10 +85,13 @@ protected:
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bool IsUAMemFast;
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/// HasVectorUAMem - True if SIMD operations can have unaligned memory
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/// operands. This may require setting a feature bit in the
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/// processor.
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/// operands. This may require setting a feature bit in the processor.
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bool HasVectorUAMem;
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/// Promote16Bit - True if codegen should promote 16-bit operations to 32-bit.
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/// This is a temporary option.
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bool Promote16Bit;
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/// DarwinVers - Nonzero if this is a darwin platform: the numeric
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/// version of the platform, e.g. 8 = 10.4 (Tiger), 9 = 10.5 (Leopard), etc.
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unsigned char DarwinVers; // Is any darwin-x86 platform.
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@ -157,6 +160,7 @@ public:
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bool isBTMemSlow() const { return IsBTMemSlow; }
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bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
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bool hasVectorUAMem() const { return HasVectorUAMem; }
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bool shouldPromote16Bit() const { return Promote16Bit; }
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bool isTargetDarwin() const { return TargetType == isDarwin; }
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bool isTargetELF() const { return TargetType == isELF; }
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