diff --git a/lib/Analysis/LiveVar/BBLiveVar.cpp b/lib/Analysis/LiveVar/BBLiveVar.cpp index 0b2979bf392..54de63e58ff 100644 --- a/lib/Analysis/LiveVar/BBLiveVar.cpp +++ b/lib/Analysis/LiveVar/BBLiveVar.cpp @@ -7,10 +7,9 @@ #include "BBLiveVar.h" #include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h" #include "llvm/CodeGen/MachineInstr.h" -#include "llvm/CodeGen/MachineCodeForBasicBlock.h" +#include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/Support/CFG.h" #include "Support/SetOperations.h" -#include /// BROKEN: Should not include sparc stuff directly into here #include "../../Target/Sparc/SparcInternals.h" // Only for PHI defn @@ -51,10 +50,10 @@ BBLiveVar::BBLiveVar(const BasicBlock &bb, unsigned id) void BBLiveVar::calcDefUseSets() { // get the iterator for machine instructions - const MachineCodeForBasicBlock &MIVec = MachineCodeForBasicBlock::get(&BB); + const MachineBasicBlock &MIVec = MachineBasicBlock::get(&BB); // iterate over all the machine instructions in BB - for (MachineCodeForBasicBlock::const_reverse_iterator MII = MIVec.rbegin(), + for (MachineBasicBlock::const_reverse_iterator MII = MIVec.rbegin(), MIE = MIVec.rend(); MII != MIE; ++MII) { const MachineInstr *MI = *MII; diff --git a/lib/Analysis/LiveVar/FunctionLiveVarInfo.cpp b/lib/Analysis/LiveVar/FunctionLiveVarInfo.cpp index e63d96c634e..198afed537c 100644 --- a/lib/Analysis/LiveVar/FunctionLiveVarInfo.cpp +++ b/lib/Analysis/LiveVar/FunctionLiveVarInfo.cpp @@ -8,12 +8,11 @@ #include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h" #include "BBLiveVar.h" #include "llvm/CodeGen/MachineInstr.h" -#include "llvm/CodeGen/MachineCodeForBasicBlock.h" +#include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/Support/CFG.h" #include "Support/PostOrderIterator.h" #include "Support/SetOperations.h" #include "Support/CommandLine.h" -#include static RegisterAnalysis X("livevar", "Live Variable Analysis"); @@ -241,7 +240,7 @@ static void applyTranferFuncForMInst(ValueSet &LVS, const MachineInstr *MInst) { //----------------------------------------------------------------------------- void FunctionLiveVarInfo::calcLiveVarSetsForBB(const BasicBlock *BB) { - const MachineCodeForBasicBlock &MIVec = MachineCodeForBasicBlock::get(BB); + const MachineBasicBlock &MIVec = MachineBasicBlock::get(BB); if (DEBUG_LV >= LV_DEBUG_Instr) std::cerr << "\n======For BB " << BB->getName() @@ -252,7 +251,7 @@ void FunctionLiveVarInfo::calcLiveVarSetsForBB(const BasicBlock *BB) { set_union(CurSet, *SetAI); // CurSet now contains OutSet // iterate over all the machine instructions in BB - for (MachineCodeForBasicBlock::const_reverse_iterator MII = MIVec.rbegin(), + for (MachineBasicBlock::const_reverse_iterator MII = MIVec.rbegin(), MIE = MIVec.rend(); MII != MIE; ++MII) { // MI is cur machine inst const MachineInstr *MI = *MII; diff --git a/lib/CodeGen/InstrSched/InstrScheduling.cpp b/lib/CodeGen/InstrSched/InstrScheduling.cpp index ea20a3e92a4..1857f893672 100644 --- a/lib/CodeGen/InstrSched/InstrScheduling.cpp +++ b/lib/CodeGen/InstrSched/InstrScheduling.cpp @@ -8,7 +8,7 @@ #include "SchedPriorities.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineCodeForInstruction.h" -#include "llvm/CodeGen/MachineCodeForBasicBlock.h" +#include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h" // FIXME: Remove when modularized better #include "llvm/Target/TargetMachine.h" @@ -631,14 +631,14 @@ AssignInstructionsToSlots(class SchedulingManager& S, unsigned maxIssue) static void RecordSchedule(const BasicBlock* bb, const SchedulingManager& S) { - MachineCodeForBasicBlock& mvec = MachineCodeForBasicBlock::get(bb); + MachineBasicBlock& mvec = MachineBasicBlock::get(bb); const MachineInstrInfo& mii = S.schedInfo.getInstrInfo(); #ifndef NDEBUG // Lets make sure we didn't lose any instructions, except possibly // some NOPs from delay slots. Also, PHIs are not included in the schedule. unsigned numInstr = 0; - for (MachineCodeForBasicBlock::iterator I=mvec.begin(); I != mvec.end(); ++I) + for (MachineBasicBlock::iterator I=mvec.begin(); I != mvec.end(); ++I) if (! mii.isNop((*I)->getOpCode()) && ! mii.isDummyPhiInstr((*I)->getOpCode())) ++numInstr; @@ -650,7 +650,7 @@ RecordSchedule(const BasicBlock* bb, const SchedulingManager& S) return; // empty basic block! // First find the dummy instructions at the start of the basic block - MachineCodeForBasicBlock::iterator I = mvec.begin(); + MachineBasicBlock::iterator I = mvec.begin(); for ( ; I != mvec.end(); ++I) if (! mii.isDummyPhiInstr((*I)->getOpCode())) break; @@ -1220,7 +1220,7 @@ ReplaceNopsWithUsefulInstr(SchedulingManager& S, // fill delay slots, otherwise, just discard them. // unsigned int firstDelaySlotIdx = node->getOrigIndexInBB() + 1; - MachineCodeForBasicBlock& bbMvec = MachineCodeForBasicBlock::get(node->getBB()); + MachineBasicBlock& bbMvec = MachineBasicBlock::get(node->getBB()); assert(bbMvec[firstDelaySlotIdx - 1] == brInstr && "Incorrect instr. index in basic block for brInstr"); @@ -1325,8 +1325,8 @@ ChooseInstructionsForDelaySlots(SchedulingManager& S, // Simply passing in an empty delayNodeVec will have this effect. // delayNodeVec.clear(); - const MachineCodeForBasicBlock& bbMvec = MachineCodeForBasicBlock::get(bb); - for (unsigned i=0; i < bbMvec.size(); i++) + const MachineBasicBlock& bbMvec = MachineBasicBlock::get(bb); + for (unsigned i=0; i < bbMvec.size(); ++i) if (bbMvec[i] != brInstr && mii.getNumDelaySlots(bbMvec[i]->getOpCode()) > 0) { diff --git a/lib/CodeGen/InstrSched/SchedGraph.cpp b/lib/CodeGen/InstrSched/SchedGraph.cpp index c3262c09df0..cc3e5b5ed4a 100644 --- a/lib/CodeGen/InstrSched/SchedGraph.cpp +++ b/lib/CodeGen/InstrSched/SchedGraph.cpp @@ -9,7 +9,7 @@ #include "SchedGraph.h" #include "llvm/CodeGen/InstrSelection.h" #include "llvm/CodeGen/MachineCodeForInstruction.h" -#include "llvm/CodeGen/MachineCodeForBasicBlock.h" +#include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/Target/MachineRegInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Function.h" @@ -387,7 +387,7 @@ SchedGraph::addCDEdges(const TerminatorInst* term, // all preceding instructions in the basic block. Use 0 latency again. // const BasicBlock* bb = firstBrNode->getBB(); - const MachineCodeForBasicBlock& mvec = MachineCodeForBasicBlock::get(bb); + const MachineBasicBlock& mvec = MachineBasicBlock::get(bb); for (unsigned i=0, N=mvec.size(); i < N; i++) { if (mvec[i] == termMvec[first]) // reached the first branch @@ -480,7 +480,7 @@ SchedGraph::addMemEdges(const vector& memNodeVec, // void SchedGraph::addCallCCEdges(const vector& memNodeVec, - MachineCodeForBasicBlock& bbMvec, + MachineBasicBlock& bbMvec, const TargetMachine& target) { const MachineInstrInfo& mii = target.getInstrInfo(); @@ -753,7 +753,7 @@ SchedGraph::buildNodesforBB(const TargetMachine& target, // Build graph nodes for each VM instruction and gather def/use info. // Do both those together in a single pass over all machine instructions. - const MachineCodeForBasicBlock& mvec = MachineCodeForBasicBlock::get(bb); + const MachineBasicBlock& mvec = MachineBasicBlock::get(bb); for (unsigned i=0; i < mvec.size(); i++) if (! mii.isDummyPhiInstr(mvec[i]->getOpCode())) { @@ -789,7 +789,7 @@ SchedGraph::buildNodesforBB(const TargetMachine& target, // Find the machine instruction that makes a copy of inval to (*PI). // This must be in the current basic block (bb). - const MachineCodeForVMInstr& mvec = MachineCodeForBasicBlock::get(*PI); + const MachineCodeForVMInstr& mvec = MachineBasicBlock::get(*PI); const MachineInstr* theCopy = NULL; for (unsigned i=0; i < mvec.size() && theCopy == NULL; i++) if (! mii.isDummyPhiInstr(mvec[i]->getOpCode())) @@ -882,7 +882,7 @@ SchedGraph::buildGraph(const TargetMachine& target) // //---------------------------------------------------------------- - MachineCodeForBasicBlock& bbMvec = MachineCodeForBasicBlock::get(bb); + MachineBasicBlock& bbMvec = MachineBasicBlock::get(bb); // First, add edges to the terminator instruction of the basic block. this->addCDEdges(bb->getTerminator(), target); diff --git a/lib/CodeGen/InstrSelection/InstrSelection.cpp b/lib/CodeGen/InstrSelection/InstrSelection.cpp index 83ce0a7dfe7..83f7927defb 100644 --- a/lib/CodeGen/InstrSelection/InstrSelection.cpp +++ b/lib/CodeGen/InstrSelection/InstrSelection.cpp @@ -11,7 +11,7 @@ #include "llvm/CodeGen/InstrSelectionSupport.h" #include "llvm/CodeGen/InstrForest.h" #include "llvm/CodeGen/MachineCodeForInstruction.h" -#include "llvm/CodeGen/MachineCodeForBasicBlock.h" +#include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/Target/MachineRegInfo.h" #include "llvm/Target/TargetMachine.h" @@ -145,7 +145,7 @@ bool InstructionSelection::runOnFunction(Function &F) for (Function::iterator BI = F.begin(), BE = F.end(); BI != BE; ++BI) for (BasicBlock::iterator II = BI->begin(); II != BI->end(); ++II) { MachineCodeForInstruction &mvec = MachineCodeForInstruction::get(II); - MachineCodeForBasicBlock &MCBB = MachineCodeForBasicBlock::get(BI); + MachineBasicBlock &MCBB = MachineBasicBlock::get(BI); MCBB.insert(MCBB.end(), mvec.begin(), mvec.end()); } @@ -205,7 +205,7 @@ InstructionSelection::InsertCodeForPhis(Function &F) Target.getRegInfo().cpValue2Value(PhiCpRes, PN, mvec); // get an iterator to machine instructions in the BB - MachineCodeForBasicBlock& bbMvec = MachineCodeForBasicBlock::get(BB); + MachineBasicBlock& bbMvec = MachineBasicBlock::get(BB); bbMvec.insert(bbMvec.begin(), mvec.begin(), mvec.end()); } // for each Phi Instr in BB @@ -227,11 +227,11 @@ InstructionSelection::InsertPhiElimInstructions(BasicBlock *BB, assert (FirstMIOfTerm && "No Machine Instrs for terminator"); - MachineCodeForBasicBlock &bbMvec = MachineCodeForBasicBlock::get(BB); + MachineBasicBlock &bbMvec = MachineBasicBlock::get(BB); // find the position of first machine instruction generated by the // terminator of this BB - MachineCodeForBasicBlock::iterator MCIt = + MachineBasicBlock::iterator MCIt = std::find(bbMvec.begin(), bbMvec.end(), FirstMIOfTerm); assert( MCIt != bbMvec.end() && "Start inst of terminator not found"); diff --git a/lib/CodeGen/MachineBasicBlock.cpp b/lib/CodeGen/MachineBasicBlock.cpp index 1b78d7a90b1..666d5477b3a 100644 --- a/lib/CodeGen/MachineBasicBlock.cpp +++ b/lib/CodeGen/MachineBasicBlock.cpp @@ -1,10 +1,10 @@ -//===-- MachineCodeForBasicBlock.cpp --------------------------------------===// +//===-- MachineBasicBlock.cpp ---------------------------------------------===// // // Collect the sequence of machine instructions for a basic block. // //===----------------------------------------------------------------------===// -#include "llvm/CodeGen/MachineCodeForBasicBlock.h" +#include "llvm/CodeGen/MachineBasicBlock.h" AnnotationID MCFBB_AID( AnnotationManager::getID("CodeGen::MachineBasicBlock")); diff --git a/lib/CodeGen/MachineFunction.cpp b/lib/CodeGen/MachineFunction.cpp index 4d680754d0f..23b8040c440 100644 --- a/lib/CodeGen/MachineFunction.cpp +++ b/lib/CodeGen/MachineFunction.cpp @@ -8,7 +8,7 @@ #include "llvm/CodeGen/MachineInstr.h" // For debug output #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineCodeForBasicBlock.h" +#include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineCodeForInstruction.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/MachineFrameInfo.h" @@ -303,7 +303,7 @@ MachineFunction::dump() const { std::cerr << "\n" << BB->getName() << " (" << (const void*)BB << ")" << ":" << "\n"; - MachineCodeForBasicBlock& mvec = MachineCodeForBasicBlock::get(BB); + MachineBasicBlock& mvec = MachineBasicBlock::get(BB); for (unsigned i=0; i < mvec.size(); i++) std::cerr << "\t" << *mvec[i]; } diff --git a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp index ea20a3e92a4..1857f893672 100644 --- a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp +++ b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp @@ -8,7 +8,7 @@ #include "SchedPriorities.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineCodeForInstruction.h" -#include "llvm/CodeGen/MachineCodeForBasicBlock.h" +#include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h" // FIXME: Remove when modularized better #include "llvm/Target/TargetMachine.h" @@ -631,14 +631,14 @@ AssignInstructionsToSlots(class SchedulingManager& S, unsigned maxIssue) static void RecordSchedule(const BasicBlock* bb, const SchedulingManager& S) { - MachineCodeForBasicBlock& mvec = MachineCodeForBasicBlock::get(bb); + MachineBasicBlock& mvec = MachineBasicBlock::get(bb); const MachineInstrInfo& mii = S.schedInfo.getInstrInfo(); #ifndef NDEBUG // Lets make sure we didn't lose any instructions, except possibly // some NOPs from delay slots. Also, PHIs are not included in the schedule. unsigned numInstr = 0; - for (MachineCodeForBasicBlock::iterator I=mvec.begin(); I != mvec.end(); ++I) + for (MachineBasicBlock::iterator I=mvec.begin(); I != mvec.end(); ++I) if (! mii.isNop((*I)->getOpCode()) && ! mii.isDummyPhiInstr((*I)->getOpCode())) ++numInstr; @@ -650,7 +650,7 @@ RecordSchedule(const BasicBlock* bb, const SchedulingManager& S) return; // empty basic block! // First find the dummy instructions at the start of the basic block - MachineCodeForBasicBlock::iterator I = mvec.begin(); + MachineBasicBlock::iterator I = mvec.begin(); for ( ; I != mvec.end(); ++I) if (! mii.isDummyPhiInstr((*I)->getOpCode())) break; @@ -1220,7 +1220,7 @@ ReplaceNopsWithUsefulInstr(SchedulingManager& S, // fill delay slots, otherwise, just discard them. // unsigned int firstDelaySlotIdx = node->getOrigIndexInBB() + 1; - MachineCodeForBasicBlock& bbMvec = MachineCodeForBasicBlock::get(node->getBB()); + MachineBasicBlock& bbMvec = MachineBasicBlock::get(node->getBB()); assert(bbMvec[firstDelaySlotIdx - 1] == brInstr && "Incorrect instr. index in basic block for brInstr"); @@ -1325,8 +1325,8 @@ ChooseInstructionsForDelaySlots(SchedulingManager& S, // Simply passing in an empty delayNodeVec will have this effect. // delayNodeVec.clear(); - const MachineCodeForBasicBlock& bbMvec = MachineCodeForBasicBlock::get(bb); - for (unsigned i=0; i < bbMvec.size(); i++) + const MachineBasicBlock& bbMvec = MachineBasicBlock::get(bb); + for (unsigned i=0; i < bbMvec.size(); ++i) if (bbMvec[i] != brInstr && mii.getNumDelaySlots(bbMvec[i]->getOpCode()) > 0) { diff --git a/lib/Target/SparcV9/InstrSched/SchedGraph.cpp b/lib/Target/SparcV9/InstrSched/SchedGraph.cpp index c3262c09df0..cc3e5b5ed4a 100644 --- a/lib/Target/SparcV9/InstrSched/SchedGraph.cpp +++ b/lib/Target/SparcV9/InstrSched/SchedGraph.cpp @@ -9,7 +9,7 @@ #include "SchedGraph.h" #include "llvm/CodeGen/InstrSelection.h" #include "llvm/CodeGen/MachineCodeForInstruction.h" -#include "llvm/CodeGen/MachineCodeForBasicBlock.h" +#include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/Target/MachineRegInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Function.h" @@ -387,7 +387,7 @@ SchedGraph::addCDEdges(const TerminatorInst* term, // all preceding instructions in the basic block. Use 0 latency again. // const BasicBlock* bb = firstBrNode->getBB(); - const MachineCodeForBasicBlock& mvec = MachineCodeForBasicBlock::get(bb); + const MachineBasicBlock& mvec = MachineBasicBlock::get(bb); for (unsigned i=0, N=mvec.size(); i < N; i++) { if (mvec[i] == termMvec[first]) // reached the first branch @@ -480,7 +480,7 @@ SchedGraph::addMemEdges(const vector& memNodeVec, // void SchedGraph::addCallCCEdges(const vector& memNodeVec, - MachineCodeForBasicBlock& bbMvec, + MachineBasicBlock& bbMvec, const TargetMachine& target) { const MachineInstrInfo& mii = target.getInstrInfo(); @@ -753,7 +753,7 @@ SchedGraph::buildNodesforBB(const TargetMachine& target, // Build graph nodes for each VM instruction and gather def/use info. // Do both those together in a single pass over all machine instructions. - const MachineCodeForBasicBlock& mvec = MachineCodeForBasicBlock::get(bb); + const MachineBasicBlock& mvec = MachineBasicBlock::get(bb); for (unsigned i=0; i < mvec.size(); i++) if (! mii.isDummyPhiInstr(mvec[i]->getOpCode())) { @@ -789,7 +789,7 @@ SchedGraph::buildNodesforBB(const TargetMachine& target, // Find the machine instruction that makes a copy of inval to (*PI). // This must be in the current basic block (bb). - const MachineCodeForVMInstr& mvec = MachineCodeForBasicBlock::get(*PI); + const MachineCodeForVMInstr& mvec = MachineBasicBlock::get(*PI); const MachineInstr* theCopy = NULL; for (unsigned i=0; i < mvec.size() && theCopy == NULL; i++) if (! mii.isDummyPhiInstr(mvec[i]->getOpCode())) @@ -882,7 +882,7 @@ SchedGraph::buildGraph(const TargetMachine& target) // //---------------------------------------------------------------- - MachineCodeForBasicBlock& bbMvec = MachineCodeForBasicBlock::get(bb); + MachineBasicBlock& bbMvec = MachineBasicBlock::get(bb); // First, add edges to the terminator instruction of the basic block. this->addCDEdges(bb->getTerminator(), target); diff --git a/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp b/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp index 83ce0a7dfe7..83f7927defb 100644 --- a/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp +++ b/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp @@ -11,7 +11,7 @@ #include "llvm/CodeGen/InstrSelectionSupport.h" #include "llvm/CodeGen/InstrForest.h" #include "llvm/CodeGen/MachineCodeForInstruction.h" -#include "llvm/CodeGen/MachineCodeForBasicBlock.h" +#include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/Target/MachineRegInfo.h" #include "llvm/Target/TargetMachine.h" @@ -145,7 +145,7 @@ bool InstructionSelection::runOnFunction(Function &F) for (Function::iterator BI = F.begin(), BE = F.end(); BI != BE; ++BI) for (BasicBlock::iterator II = BI->begin(); II != BI->end(); ++II) { MachineCodeForInstruction &mvec = MachineCodeForInstruction::get(II); - MachineCodeForBasicBlock &MCBB = MachineCodeForBasicBlock::get(BI); + MachineBasicBlock &MCBB = MachineBasicBlock::get(BI); MCBB.insert(MCBB.end(), mvec.begin(), mvec.end()); } @@ -205,7 +205,7 @@ InstructionSelection::InsertCodeForPhis(Function &F) Target.getRegInfo().cpValue2Value(PhiCpRes, PN, mvec); // get an iterator to machine instructions in the BB - MachineCodeForBasicBlock& bbMvec = MachineCodeForBasicBlock::get(BB); + MachineBasicBlock& bbMvec = MachineBasicBlock::get(BB); bbMvec.insert(bbMvec.begin(), mvec.begin(), mvec.end()); } // for each Phi Instr in BB @@ -227,11 +227,11 @@ InstructionSelection::InsertPhiElimInstructions(BasicBlock *BB, assert (FirstMIOfTerm && "No Machine Instrs for terminator"); - MachineCodeForBasicBlock &bbMvec = MachineCodeForBasicBlock::get(BB); + MachineBasicBlock &bbMvec = MachineBasicBlock::get(BB); // find the position of first machine instruction generated by the // terminator of this BB - MachineCodeForBasicBlock::iterator MCIt = + MachineBasicBlock::iterator MCIt = std::find(bbMvec.begin(), bbMvec.end(), FirstMIOfTerm); assert( MCIt != bbMvec.end() && "Start inst of terminator not found"); diff --git a/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp b/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp index 0b2979bf392..54de63e58ff 100644 --- a/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp +++ b/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp @@ -7,10 +7,9 @@ #include "BBLiveVar.h" #include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h" #include "llvm/CodeGen/MachineInstr.h" -#include "llvm/CodeGen/MachineCodeForBasicBlock.h" +#include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/Support/CFG.h" #include "Support/SetOperations.h" -#include /// BROKEN: Should not include sparc stuff directly into here #include "../../Target/Sparc/SparcInternals.h" // Only for PHI defn @@ -51,10 +50,10 @@ BBLiveVar::BBLiveVar(const BasicBlock &bb, unsigned id) void BBLiveVar::calcDefUseSets() { // get the iterator for machine instructions - const MachineCodeForBasicBlock &MIVec = MachineCodeForBasicBlock::get(&BB); + const MachineBasicBlock &MIVec = MachineBasicBlock::get(&BB); // iterate over all the machine instructions in BB - for (MachineCodeForBasicBlock::const_reverse_iterator MII = MIVec.rbegin(), + for (MachineBasicBlock::const_reverse_iterator MII = MIVec.rbegin(), MIE = MIVec.rend(); MII != MIE; ++MII) { const MachineInstr *MI = *MII; diff --git a/lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp b/lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp index e63d96c634e..198afed537c 100644 --- a/lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp +++ b/lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp @@ -8,12 +8,11 @@ #include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h" #include "BBLiveVar.h" #include "llvm/CodeGen/MachineInstr.h" -#include "llvm/CodeGen/MachineCodeForBasicBlock.h" +#include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/Support/CFG.h" #include "Support/PostOrderIterator.h" #include "Support/SetOperations.h" #include "Support/CommandLine.h" -#include static RegisterAnalysis X("livevar", "Live Variable Analysis"); @@ -241,7 +240,7 @@ static void applyTranferFuncForMInst(ValueSet &LVS, const MachineInstr *MInst) { //----------------------------------------------------------------------------- void FunctionLiveVarInfo::calcLiveVarSetsForBB(const BasicBlock *BB) { - const MachineCodeForBasicBlock &MIVec = MachineCodeForBasicBlock::get(BB); + const MachineBasicBlock &MIVec = MachineBasicBlock::get(BB); if (DEBUG_LV >= LV_DEBUG_Instr) std::cerr << "\n======For BB " << BB->getName() @@ -252,7 +251,7 @@ void FunctionLiveVarInfo::calcLiveVarSetsForBB(const BasicBlock *BB) { set_union(CurSet, *SetAI); // CurSet now contains OutSet // iterate over all the machine instructions in BB - for (MachineCodeForBasicBlock::const_reverse_iterator MII = MIVec.rbegin(), + for (MachineBasicBlock::const_reverse_iterator MII = MIVec.rbegin(), MIE = MIVec.rend(); MII != MIE; ++MII) { // MI is cur machine inst const MachineInstr *MI = *MII; diff --git a/lib/Target/SparcV9/MappingInfo.cpp b/lib/Target/SparcV9/MappingInfo.cpp index e207c20f2e0..087fba20595 100644 --- a/lib/Target/SparcV9/MappingInfo.cpp +++ b/lib/Target/SparcV9/MappingInfo.cpp @@ -10,7 +10,7 @@ #include "llvm/Pass.h" #include "llvm/Module.h" #include "llvm/CodeGen/MachineInstr.h" -#include "llvm/CodeGen/MachineCodeForBasicBlock.h" +#include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineCodeForInstruction.h" #include using std::vector; @@ -126,7 +126,7 @@ void getMappingInfoForFunction::create_BB_to_MInumber_Key(Function &FI){ unsigned i = 0; for (Function::iterator BI = FI.begin(), BE = FI.end(); BI != BE; ++BI){ - MachineCodeForBasicBlock &miBB = MachineCodeForBasicBlock::get(BI); + MachineBasicBlock &miBB = MachineBasicBlock::get(BI); BBkey[miBB[0]] = i; i = i+(miBB.size()); } @@ -136,9 +136,9 @@ void getMappingInfoForFunction::create_BB_to_MInumber_Key(Function &FI){ void getMappingInfoForFunction::create_MI_to_number_Key(Function &FI){ for (Function::iterator BI=FI.begin(), BE=FI.end(); BI != BE; ++BI){ - MachineCodeForBasicBlock &miBB = MachineCodeForBasicBlock::get(BI); + MachineBasicBlock &miBB = MachineBasicBlock::get(BI); unsigned j = 0; - for(MachineCodeForBasicBlock::iterator miI=miBB.begin(), miE=miBB.end(); + for(MachineBasicBlock::iterator miI=miBB.begin(), miE=miBB.end(); miI!=miE; ++miI, ++j){ MIkey[*miI]=j; } @@ -151,7 +151,7 @@ void getMappingInfoForFunction::writeBBToMImap(Function &FI){ unsigned bb=0; for (Function::iterator BI = FI.begin(), BE = FI.end(); BI != BE; ++BI, ++bb){ - MachineCodeForBasicBlock &miBB = MachineCodeForBasicBlock::get(BI); + MachineBasicBlock &miBB = MachineBasicBlock::get(BI); writeNumber(bb); //Out << " BB: "<<(void *)BI<<"\n"; //for(int i=0; iSetMachineOperandReg(2, Target.getRegInfo().getZeroRegNum()); - MachineCodeForBasicBlock& bbMvec = MachineCodeForBasicBlock::get(I); + MachineBasicBlock& bbMvec = MachineBasicBlock::get(I); MachineCodeForInstruction &termMvec = MachineCodeForInstruction::get(TermInst);