mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-04-16 20:40:16 +00:00
Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enums
from ARMRegisterInfo.h git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104508 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
parent
3458e9e4df
commit
558661d271
@ -834,10 +834,10 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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// spilled def has a sub-register index.
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MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VST2q32))
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.addFrameIndex(FI).addImm(128);
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MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_0, getKillRegState(isKill), TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_1, 0, TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_2, 0, TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_3, 0, TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
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AddDefaultPred(MIB.addMemOperand(MMO));
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} else {
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MachineInstrBuilder MIB =
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@ -845,10 +845,10 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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.addFrameIndex(FI)
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.addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
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.addMemOperand(MMO);
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MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_0, getKillRegState(isKill), TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_1, 0, TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_2, 0, TRI);
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AddDReg(MIB, SrcReg, ARM::DSUBREG_3, 0, TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
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AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
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}
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} else {
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assert(RC == ARM::QQQQPRRegisterClass && "Unknown regclass!");
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@ -857,14 +857,14 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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.addFrameIndex(FI)
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.addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
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.addMemOperand(MMO);
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MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_0, getKillRegState(isKill), TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_1, 0, TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_2, 0, TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_3, 0, TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_4, 0, TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_5, 0, TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_6, 0, TRI);
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AddDReg(MIB, SrcReg, ARM::DSUBREG_7, 0, TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
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AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
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}
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}
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@ -916,10 +916,10 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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} else if (RC == ARM::QQPRRegisterClass || RC == ARM::QQPR_VFP2RegisterClass){
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if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
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MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLD2q32));
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MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_0, RegState::Define, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_1, RegState::Define, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_2, RegState::Define, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_3, RegState::Define, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
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AddDefaultPred(MIB.addFrameIndex(FI).addImm(128).addMemOperand(MMO));
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} else {
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MachineInstrBuilder MIB =
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@ -927,10 +927,10 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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.addFrameIndex(FI)
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.addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
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.addMemOperand(MMO);
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MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_0, RegState::Define, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_1, RegState::Define, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_2, RegState::Define, TRI);
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AddDReg(MIB, DestReg, ARM::DSUBREG_3, RegState::Define, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
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AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
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}
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} else {
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assert(RC == ARM::QQQQPRRegisterClass && "Unknown regclass!");
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@ -939,14 +939,14 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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.addFrameIndex(FI)
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.addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
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.addMemOperand(MMO);
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MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_0, RegState::Define, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_1, RegState::Define, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_2, RegState::Define, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_3, RegState::Define, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_4, RegState::Define, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_5, RegState::Define, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_6, RegState::Define, TRI);
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AddDReg(MIB, DestReg, ARM::DSUBREG_7, RegState::Define, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI);
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AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI);
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}
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}
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@ -365,101 +365,101 @@ ARMBaseRegisterInfo::canCombinedSubRegIndex(const TargetRegisterClass *RC,
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if (NumRegs == 8) {
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// 8 D registers -> 1 QQQQ register.
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return (Size == 512 &&
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SubIndices[0] == ARM::DSUBREG_0 &&
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SubIndices[1] == ARM::DSUBREG_1 &&
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SubIndices[2] == ARM::DSUBREG_2 &&
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SubIndices[3] == ARM::DSUBREG_3 &&
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SubIndices[4] == ARM::DSUBREG_4 &&
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SubIndices[5] == ARM::DSUBREG_5 &&
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SubIndices[6] == ARM::DSUBREG_6 &&
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SubIndices[7] == ARM::DSUBREG_7);
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SubIndices[0] == ARM::dsub_0 &&
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SubIndices[1] == ARM::dsub_1 &&
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SubIndices[2] == ARM::dsub_2 &&
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SubIndices[3] == ARM::dsub_3 &&
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SubIndices[4] == ARM::dsub_4 &&
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SubIndices[5] == ARM::dsub_5 &&
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SubIndices[6] == ARM::dsub_6 &&
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SubIndices[7] == ARM::dsub_7);
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} else if (NumRegs == 4) {
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if (SubIndices[0] == ARM::QSUBREG_0) {
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if (SubIndices[0] == ARM::qsub_0) {
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// 4 Q registers -> 1 QQQQ register.
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return (Size == 512 &&
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SubIndices[1] == ARM::QSUBREG_1 &&
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SubIndices[2] == ARM::QSUBREG_2 &&
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SubIndices[3] == ARM::QSUBREG_3);
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} else if (SubIndices[0] == ARM::DSUBREG_0) {
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SubIndices[1] == ARM::qsub_1 &&
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SubIndices[2] == ARM::qsub_2 &&
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SubIndices[3] == ARM::qsub_3);
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} else if (SubIndices[0] == ARM::dsub_0) {
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// 4 D registers -> 1 QQ register.
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if (Size >= 256 &&
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SubIndices[1] == ARM::DSUBREG_1 &&
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SubIndices[2] == ARM::DSUBREG_2 &&
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SubIndices[3] == ARM::DSUBREG_3) {
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SubIndices[1] == ARM::dsub_1 &&
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SubIndices[2] == ARM::dsub_2 &&
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SubIndices[3] == ARM::dsub_3) {
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if (Size == 512)
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NewSubIdx = ARM::QQSUBREG_0;
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NewSubIdx = ARM::qqsub_0;
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return true;
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}
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} else if (SubIndices[0] == ARM::DSUBREG_4) {
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} else if (SubIndices[0] == ARM::dsub_4) {
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// 4 D registers -> 1 QQ register (2nd).
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if (Size == 512 &&
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SubIndices[1] == ARM::DSUBREG_5 &&
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SubIndices[2] == ARM::DSUBREG_6 &&
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SubIndices[3] == ARM::DSUBREG_7) {
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NewSubIdx = ARM::QQSUBREG_1;
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SubIndices[1] == ARM::dsub_5 &&
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SubIndices[2] == ARM::dsub_6 &&
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SubIndices[3] == ARM::dsub_7) {
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NewSubIdx = ARM::qqsub_1;
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return true;
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}
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} else if (SubIndices[0] == ARM::SSUBREG_0) {
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} else if (SubIndices[0] == ARM::ssub_0) {
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// 4 S registers -> 1 Q register.
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if (Size >= 128 &&
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SubIndices[1] == ARM::SSUBREG_1 &&
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SubIndices[2] == ARM::SSUBREG_2 &&
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SubIndices[3] == ARM::SSUBREG_3) {
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SubIndices[1] == ARM::ssub_1 &&
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SubIndices[2] == ARM::ssub_2 &&
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SubIndices[3] == ARM::ssub_3) {
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if (Size >= 256)
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NewSubIdx = ARM::QSUBREG_0;
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NewSubIdx = ARM::qsub_0;
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return true;
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}
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}
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} else if (NumRegs == 2) {
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if (SubIndices[0] == ARM::QSUBREG_0) {
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if (SubIndices[0] == ARM::qsub_0) {
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// 2 Q registers -> 1 QQ register.
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if (Size >= 256 && SubIndices[1] == ARM::QSUBREG_1) {
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if (Size >= 256 && SubIndices[1] == ARM::qsub_1) {
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if (Size == 512)
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NewSubIdx = ARM::QQSUBREG_0;
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NewSubIdx = ARM::qqsub_0;
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return true;
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}
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} else if (SubIndices[0] == ARM::QSUBREG_2) {
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} else if (SubIndices[0] == ARM::qsub_2) {
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// 2 Q registers -> 1 QQ register (2nd).
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if (Size == 512 && SubIndices[1] == ARM::QSUBREG_3) {
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NewSubIdx = ARM::QQSUBREG_1;
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if (Size == 512 && SubIndices[1] == ARM::qsub_3) {
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NewSubIdx = ARM::qqsub_1;
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return true;
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}
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} else if (SubIndices[0] == ARM::DSUBREG_0) {
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} else if (SubIndices[0] == ARM::dsub_0) {
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// 2 D registers -> 1 Q register.
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if (Size >= 128 && SubIndices[1] == ARM::DSUBREG_1) {
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if (Size >= 128 && SubIndices[1] == ARM::dsub_1) {
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if (Size >= 256)
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NewSubIdx = ARM::QSUBREG_0;
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NewSubIdx = ARM::qsub_0;
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return true;
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}
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} else if (SubIndices[0] == ARM::DSUBREG_2) {
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} else if (SubIndices[0] == ARM::dsub_2) {
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// 2 D registers -> 1 Q register (2nd).
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if (Size >= 256 && SubIndices[1] == ARM::DSUBREG_3) {
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NewSubIdx = ARM::QSUBREG_1;
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if (Size >= 256 && SubIndices[1] == ARM::dsub_3) {
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NewSubIdx = ARM::qsub_1;
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return true;
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}
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} else if (SubIndices[0] == ARM::DSUBREG_4) {
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} else if (SubIndices[0] == ARM::dsub_4) {
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// 2 D registers -> 1 Q register (3rd).
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if (Size == 512 && SubIndices[1] == ARM::DSUBREG_5) {
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NewSubIdx = ARM::QSUBREG_2;
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if (Size == 512 && SubIndices[1] == ARM::dsub_5) {
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NewSubIdx = ARM::qsub_2;
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return true;
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}
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} else if (SubIndices[0] == ARM::DSUBREG_6) {
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} else if (SubIndices[0] == ARM::dsub_6) {
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// 2 D registers -> 1 Q register (3rd).
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if (Size == 512 && SubIndices[1] == ARM::DSUBREG_7) {
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NewSubIdx = ARM::QSUBREG_3;
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if (Size == 512 && SubIndices[1] == ARM::dsub_7) {
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NewSubIdx = ARM::qsub_3;
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return true;
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}
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} else if (SubIndices[0] == ARM::SSUBREG_0) {
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} else if (SubIndices[0] == ARM::ssub_0) {
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// 2 S registers -> 1 D register.
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if (SubIndices[1] == ARM::SSUBREG_1) {
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if (SubIndices[1] == ARM::ssub_1) {
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if (Size >= 128)
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NewSubIdx = ARM::DSUBREG_0;
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NewSubIdx = ARM::dsub_0;
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return true;
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}
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} else if (SubIndices[0] == ARM::SSUBREG_2) {
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} else if (SubIndices[0] == ARM::ssub_2) {
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// 2 S registers -> 1 D register (2nd).
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if (Size >= 128 && SubIndices[1] == ARM::SSUBREG_3) {
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NewSubIdx = ARM::DSUBREG_1;
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if (Size >= 128 && SubIndices[1] == ARM::ssub_3) {
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NewSubIdx = ARM::dsub_1;
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return true;
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}
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}
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@ -135,12 +135,12 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
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case ARM::VMOVQQ: {
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unsigned DstReg = MI.getOperand(0).getReg();
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bool DstIsDead = MI.getOperand(0).isDead();
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unsigned EvenDst = TRI->getSubReg(DstReg, ARM::QSUBREG_0);
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unsigned OddDst = TRI->getSubReg(DstReg, ARM::QSUBREG_1);
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unsigned EvenDst = TRI->getSubReg(DstReg, ARM::qsub_0);
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unsigned OddDst = TRI->getSubReg(DstReg, ARM::qsub_1);
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unsigned SrcReg = MI.getOperand(1).getReg();
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bool SrcIsKill = MI.getOperand(1).isKill();
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unsigned EvenSrc = TRI->getSubReg(SrcReg, ARM::QSUBREG_0);
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unsigned OddSrc = TRI->getSubReg(SrcReg, ARM::QSUBREG_1);
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unsigned EvenSrc = TRI->getSubReg(SrcReg, ARM::qsub_0);
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unsigned OddSrc = TRI->getSubReg(SrcReg, ARM::qsub_1);
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MachineInstrBuilder Even =
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AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
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TII->get(ARM::VMOVQ))
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@ -964,8 +964,8 @@ SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) {
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///
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SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
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DebugLoc dl = V0.getNode()->getDebugLoc();
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SDValue SubReg0 = CurDAG->getTargetConstant(ARM::DSUBREG_0, MVT::i32);
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SDValue SubReg1 = CurDAG->getTargetConstant(ARM::DSUBREG_1, MVT::i32);
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SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
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SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
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if (llvm::ModelWithRegSequence()) {
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const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
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return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
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@ -982,8 +982,8 @@ SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
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///
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SDNode *ARMDAGToDAGISel::PairQRegs(EVT VT, SDValue V0, SDValue V1) {
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DebugLoc dl = V0.getNode()->getDebugLoc();
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SDValue SubReg0 = CurDAG->getTargetConstant(ARM::QSUBREG_0, MVT::i32);
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SDValue SubReg1 = CurDAG->getTargetConstant(ARM::QSUBREG_1, MVT::i32);
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SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
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SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
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const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
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return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
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}
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@ -993,10 +993,10 @@ SDNode *ARMDAGToDAGISel::PairQRegs(EVT VT, SDValue V0, SDValue V1) {
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SDNode *ARMDAGToDAGISel::QuadDRegs(EVT VT, SDValue V0, SDValue V1,
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SDValue V2, SDValue V3) {
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DebugLoc dl = V0.getNode()->getDebugLoc();
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SDValue SubReg0 = CurDAG->getTargetConstant(ARM::DSUBREG_0, MVT::i32);
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SDValue SubReg1 = CurDAG->getTargetConstant(ARM::DSUBREG_1, MVT::i32);
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SDValue SubReg2 = CurDAG->getTargetConstant(ARM::DSUBREG_2, MVT::i32);
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SDValue SubReg3 = CurDAG->getTargetConstant(ARM::DSUBREG_3, MVT::i32);
|
||||
SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
|
||||
SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
|
||||
SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32);
|
||||
SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32);
|
||||
const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
|
||||
return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
|
||||
}
|
||||
@ -1006,10 +1006,10 @@ SDNode *ARMDAGToDAGISel::QuadDRegs(EVT VT, SDValue V0, SDValue V1,
|
||||
SDNode *ARMDAGToDAGISel::QuadQRegs(EVT VT, SDValue V0, SDValue V1,
|
||||
SDValue V2, SDValue V3) {
|
||||
DebugLoc dl = V0.getNode()->getDebugLoc();
|
||||
SDValue SubReg0 = CurDAG->getTargetConstant(ARM::QSUBREG_0, MVT::i32);
|
||||
SDValue SubReg1 = CurDAG->getTargetConstant(ARM::QSUBREG_1, MVT::i32);
|
||||
SDValue SubReg2 = CurDAG->getTargetConstant(ARM::QSUBREG_2, MVT::i32);
|
||||
SDValue SubReg3 = CurDAG->getTargetConstant(ARM::QSUBREG_3, MVT::i32);
|
||||
SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
|
||||
SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
|
||||
SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, MVT::i32);
|
||||
SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, MVT::i32);
|
||||
const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
|
||||
return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
|
||||
}
|
||||
@ -1021,14 +1021,14 @@ SDNode *ARMDAGToDAGISel::OctoDRegs(EVT VT, SDValue V0, SDValue V1,
|
||||
SDValue V4, SDValue V5,
|
||||
SDValue V6, SDValue V7) {
|
||||
DebugLoc dl = V0.getNode()->getDebugLoc();
|
||||
SDValue SubReg0 = CurDAG->getTargetConstant(ARM::DSUBREG_0, MVT::i32);
|
||||
SDValue SubReg1 = CurDAG->getTargetConstant(ARM::DSUBREG_1, MVT::i32);
|
||||
SDValue SubReg2 = CurDAG->getTargetConstant(ARM::DSUBREG_2, MVT::i32);
|
||||
SDValue SubReg3 = CurDAG->getTargetConstant(ARM::DSUBREG_3, MVT::i32);
|
||||
SDValue SubReg4 = CurDAG->getTargetConstant(ARM::DSUBREG_4, MVT::i32);
|
||||
SDValue SubReg5 = CurDAG->getTargetConstant(ARM::DSUBREG_5, MVT::i32);
|
||||
SDValue SubReg6 = CurDAG->getTargetConstant(ARM::DSUBREG_6, MVT::i32);
|
||||
SDValue SubReg7 = CurDAG->getTargetConstant(ARM::DSUBREG_7, MVT::i32);
|
||||
SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
|
||||
SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
|
||||
SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32);
|
||||
SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32);
|
||||
SDValue SubReg4 = CurDAG->getTargetConstant(ARM::dsub_4, MVT::i32);
|
||||
SDValue SubReg5 = CurDAG->getTargetConstant(ARM::dsub_5, MVT::i32);
|
||||
SDValue SubReg6 = CurDAG->getTargetConstant(ARM::dsub_6, MVT::i32);
|
||||
SDValue SubReg7 = CurDAG->getTargetConstant(ARM::dsub_7, MVT::i32);
|
||||
const SDValue Ops[] ={ V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3,
|
||||
V4, SubReg4, V5, SubReg5, V6, SubReg6, V7, SubReg7 };
|
||||
return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 16);
|
||||
@ -1108,7 +1108,7 @@ SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, unsigned NumVecs,
|
||||
}
|
||||
|
||||
for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
|
||||
SDValue D = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0+Vec,
|
||||
SDValue D = CurDAG->getTargetExtractSubreg(ARM::dsub_0+Vec,
|
||||
dl, VT, RegSeq);
|
||||
ReplaceUses(SDValue(N, Vec), D);
|
||||
}
|
||||
@ -1136,8 +1136,8 @@ SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, unsigned NumVecs,
|
||||
SDValue QQ = SDValue(QuadDRegs(MVT::v4i64,
|
||||
SDValue(VLd, 0), SDValue(VLd, 1),
|
||||
SDValue(VLd, 2), SDValue(VLd, 3)), 0);
|
||||
SDValue Q0 = CurDAG->getTargetExtractSubreg(ARM::QSUBREG_0, dl, VT, QQ);
|
||||
SDValue Q1 = CurDAG->getTargetExtractSubreg(ARM::QSUBREG_1, dl, VT, QQ);
|
||||
SDValue Q0 = CurDAG->getTargetExtractSubreg(ARM::qsub_0, dl, VT, QQ);
|
||||
SDValue Q1 = CurDAG->getTargetExtractSubreg(ARM::qsub_1, dl, VT, QQ);
|
||||
ReplaceUses(SDValue(N, 0), Q0);
|
||||
ReplaceUses(SDValue(N, 1), Q1);
|
||||
}
|
||||
@ -1188,7 +1188,7 @@ SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, unsigned NumVecs,
|
||||
|
||||
// Extract out the 3 / 4 Q registers.
|
||||
for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
|
||||
SDValue Q = CurDAG->getTargetExtractSubreg(ARM::QSUBREG_0+Vec,
|
||||
SDValue Q = CurDAG->getTargetExtractSubreg(ARM::qsub_0+Vec,
|
||||
dl, VT, RegSeq);
|
||||
ReplaceUses(SDValue(N, Vec), Q);
|
||||
}
|
||||
@ -1264,15 +1264,15 @@ SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
|
||||
}
|
||||
|
||||
// Now extract the D registers back out.
|
||||
Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, VT,
|
||||
Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, VT,
|
||||
RegSeq));
|
||||
Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, VT,
|
||||
Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, VT,
|
||||
RegSeq));
|
||||
if (NumVecs > 2)
|
||||
Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_2, dl, VT,
|
||||
Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_2, dl, VT,
|
||||
RegSeq));
|
||||
if (NumVecs > 3)
|
||||
Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_3, dl, VT,
|
||||
Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_3, dl, VT,
|
||||
RegSeq));
|
||||
} else {
|
||||
for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
|
||||
@ -1299,13 +1299,13 @@ SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
|
||||
SDValue QQ = SDValue(PairQRegs(MVT::v4i64, Q0, Q1), 0);
|
||||
|
||||
// Now extract the D registers back out.
|
||||
Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
|
||||
Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, RegVT,
|
||||
QQ));
|
||||
Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
|
||||
Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, RegVT,
|
||||
QQ));
|
||||
Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_2, dl, RegVT,
|
||||
Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_2, dl, RegVT,
|
||||
QQ));
|
||||
Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_3, dl, RegVT,
|
||||
Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_3, dl, RegVT,
|
||||
QQ));
|
||||
Ops.push_back(Pred);
|
||||
Ops.push_back(Reg0); // predicate register
|
||||
@ -1313,9 +1313,9 @@ SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
|
||||
return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 5 + 4);
|
||||
} else {
|
||||
for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
|
||||
Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
|
||||
Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, RegVT,
|
||||
N->getOperand(Vec+3)));
|
||||
Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
|
||||
Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, RegVT,
|
||||
N->getOperand(Vec+3)));
|
||||
}
|
||||
Ops.push_back(Pred);
|
||||
@ -1332,9 +1332,9 @@ SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
|
||||
// Form the QQQQ REG_SEQUENCE.
|
||||
SDValue V[8];
|
||||
for (unsigned Vec = 0, i = 0; Vec < NumVecs; ++Vec, i+=2) {
|
||||
V[i] = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
|
||||
V[i] = CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, RegVT,
|
||||
N->getOperand(Vec+3));
|
||||
V[i+1] = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
|
||||
V[i+1] = CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, RegVT,
|
||||
N->getOperand(Vec+3));
|
||||
}
|
||||
if (NumVecs == 3)
|
||||
@ -1347,7 +1347,7 @@ SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
|
||||
// Store the even D registers.
|
||||
Ops.push_back(Reg0); // post-access address offset
|
||||
for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
|
||||
Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0+Vec*2, dl,
|
||||
Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0+Vec*2, dl,
|
||||
RegVT, RegSeq));
|
||||
Ops.push_back(Pred);
|
||||
Ops.push_back(Reg0); // predicate register
|
||||
@ -1360,7 +1360,7 @@ SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
|
||||
// Store the odd D registers.
|
||||
Ops[0] = SDValue(VStA, 0); // MemAddr
|
||||
for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
|
||||
Ops[Vec+3] = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1+Vec*2, dl,
|
||||
Ops[Vec+3] = CurDAG->getTargetExtractSubreg(ARM::dsub_1+Vec*2, dl,
|
||||
RegVT, RegSeq);
|
||||
Ops[NumVecs+5] = Chain;
|
||||
Opc = QOpcodes1[OpcodeIndex];
|
||||
@ -1374,7 +1374,7 @@ SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
|
||||
|
||||
// Store the even subregs.
|
||||
for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
|
||||
Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
|
||||
Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, RegVT,
|
||||
N->getOperand(Vec+3)));
|
||||
Ops.push_back(Pred);
|
||||
Ops.push_back(Reg0); // predicate register
|
||||
@ -1387,7 +1387,7 @@ SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
|
||||
// Store the odd subregs.
|
||||
Ops[0] = SDValue(VStA, 0); // MemAddr
|
||||
for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
|
||||
Ops[Vec+3] = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
|
||||
Ops[Vec+3] = CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, RegVT,
|
||||
N->getOperand(Vec+3));
|
||||
Ops[NumVecs+5] = Chain;
|
||||
Opc = QOpcodes1[OpcodeIndex];
|
||||
@ -1424,7 +1424,7 @@ SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
|
||||
if (!is64BitVector) {
|
||||
RegVT = GetNEONSubregVT(VT);
|
||||
NumElts = RegVT.getVectorNumElements();
|
||||
SubregIdx = (Lane < NumElts) ? ARM::DSUBREG_0 : ARM::DSUBREG_1;
|
||||
SubregIdx = (Lane < NumElts) ? ARM::dsub_0 : ARM::dsub_1;
|
||||
Even = Lane < NumElts;
|
||||
}
|
||||
|
||||
@ -1467,15 +1467,15 @@ SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
|
||||
}
|
||||
|
||||
// Now extract the D registers back out.
|
||||
Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, VT,
|
||||
Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, VT,
|
||||
RegSeq));
|
||||
Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, VT,
|
||||
Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, VT,
|
||||
RegSeq));
|
||||
if (NumVecs > 2)
|
||||
Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_2, dl, VT,
|
||||
Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_2, dl, VT,
|
||||
RegSeq));
|
||||
if (NumVecs > 3)
|
||||
Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_3, dl, VT,
|
||||
Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_3, dl, VT,
|
||||
RegSeq));
|
||||
} else {
|
||||
for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
|
||||
@ -1505,7 +1505,7 @@ SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
|
||||
}
|
||||
|
||||
// Extract the subregs of the input vector.
|
||||
unsigned SubIdx = Even ? ARM::DSUBREG_0 : ARM::DSUBREG_1;
|
||||
unsigned SubIdx = Even ? ARM::dsub_0 : ARM::dsub_1;
|
||||
for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
|
||||
Ops.push_back(CurDAG->getTargetExtractSubreg(SubIdx+Vec*2, dl, RegVT,
|
||||
RegSeq));
|
||||
@ -1570,7 +1570,7 @@ SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
|
||||
V[4], V[5], V[6], V[7]), 0);
|
||||
}
|
||||
|
||||
unsigned SubIdx = is64BitVector ? ARM::DSUBREG_0 : ARM::QSUBREG_0;
|
||||
unsigned SubIdx = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
|
||||
for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
|
||||
ReplaceUses(SDValue(N, Vec),
|
||||
CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, RegSeq));
|
||||
@ -1830,8 +1830,8 @@ SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
|
||||
DebugLoc dl = N->getDebugLoc();
|
||||
SDValue V0 = N->getOperand(0);
|
||||
SDValue V1 = N->getOperand(1);
|
||||
SDValue SubReg0 = CurDAG->getTargetConstant(ARM::DSUBREG_0, MVT::i32);
|
||||
SDValue SubReg1 = CurDAG->getTargetConstant(ARM::DSUBREG_1, MVT::i32);
|
||||
SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
|
||||
SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
|
||||
const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
|
||||
return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
|
||||
}
|
||||
|
||||
@ -796,7 +796,7 @@ def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32">;
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Extract D sub-registers of Q registers.
|
||||
// (arm_dsubreg_0 is 5; arm_dsubreg_1 is 6)
|
||||
// (dsub_0 is 5; dsub_1 is 6)
|
||||
def DSubReg_i8_reg : SDNodeXForm<imm, [{
|
||||
return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32);
|
||||
}]>;
|
||||
@ -814,7 +814,7 @@ def DSubReg_f64_other_reg : SDNodeXForm<imm, [{
|
||||
}]>;
|
||||
|
||||
// Extract S sub-registers of Q/D registers.
|
||||
// (arm_ssubreg_0 is 1; arm_ssubreg_1 is 2; etc.)
|
||||
// (ssub_0 is 1; ssub_1 is 2; etc.)
|
||||
def SSubReg_f32_reg : SDNodeXForm<imm, [{
|
||||
return CurDAG->getTargetConstant(1 + N->getZExtValue(), MVT::i32);
|
||||
}]>;
|
||||
@ -3011,11 +3011,11 @@ def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
|
||||
(INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
|
||||
|
||||
def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
|
||||
(INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>;
|
||||
(INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
|
||||
def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
|
||||
(INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, arm_dsubreg_0)>;
|
||||
(INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
|
||||
def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
|
||||
(INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>;
|
||||
(INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
|
||||
|
||||
def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
|
||||
(VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
|
||||
@ -3027,15 +3027,15 @@ def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
|
||||
def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
|
||||
(INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
|
||||
(VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
|
||||
arm_dsubreg_0)>;
|
||||
dsub_0)>;
|
||||
def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
|
||||
(INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
|
||||
(VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
|
||||
arm_dsubreg_0)>;
|
||||
dsub_0)>;
|
||||
def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
|
||||
(INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
|
||||
(VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
|
||||
arm_dsubreg_0)>;
|
||||
dsub_0)>;
|
||||
|
||||
// VDUP : Vector Duplicate (from ARM core register to all elements)
|
||||
|
||||
@ -3369,27 +3369,27 @@ def VTBX4
|
||||
class N2VSPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
|
||||
: NEONFPPat<(ResTy (OpNode SPR:$a)),
|
||||
(EXTRACT_SUBREG (OpTy (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)),
|
||||
SPR:$a, arm_ssubreg_0))),
|
||||
arm_ssubreg_0)>;
|
||||
SPR:$a, ssub_0))),
|
||||
ssub_0)>;
|
||||
|
||||
class N3VSPat<SDNode OpNode, NeonI Inst>
|
||||
: NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
|
||||
(EXTRACT_SUBREG (v2f32
|
||||
(Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
|
||||
SPR:$a, arm_ssubreg_0),
|
||||
SPR:$a, ssub_0),
|
||||
(INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
|
||||
SPR:$b, arm_ssubreg_0))),
|
||||
arm_ssubreg_0)>;
|
||||
SPR:$b, ssub_0))),
|
||||
ssub_0)>;
|
||||
|
||||
class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
|
||||
: NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
|
||||
(EXTRACT_SUBREG (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
|
||||
SPR:$acc, arm_ssubreg_0),
|
||||
SPR:$acc, ssub_0),
|
||||
(INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
|
||||
SPR:$a, arm_ssubreg_0),
|
||||
SPR:$a, ssub_0),
|
||||
(INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
|
||||
SPR:$b, arm_ssubreg_0)),
|
||||
arm_ssubreg_0)>;
|
||||
SPR:$b, ssub_0)),
|
||||
ssub_0)>;
|
||||
|
||||
// These need separate instructions because they must use DPR_VFP2 register
|
||||
// class which have SPR sub-registers.
|
||||
|
||||
@ -23,19 +23,6 @@ namespace llvm {
|
||||
class ARMBaseInstrInfo;
|
||||
class Type;
|
||||
|
||||
namespace ARM {
|
||||
/// SubregIndex - The index of various subregister classes. Note that
|
||||
/// these indices must be kept in sync with the class indices in the
|
||||
/// ARMRegisterInfo.td file.
|
||||
enum SubregIndex {
|
||||
SSUBREG_0 = 1, SSUBREG_1 = 2, SSUBREG_2 = 3, SSUBREG_3 = 4,
|
||||
DSUBREG_0 = 5, DSUBREG_1 = 6, DSUBREG_2 = 7, DSUBREG_3 = 8,
|
||||
DSUBREG_4 = 9, DSUBREG_5 = 10, DSUBREG_6 = 11, DSUBREG_7 = 12,
|
||||
QSUBREG_0 = 13, QSUBREG_1 = 14, QSUBREG_2 = 15, QSUBREG_3 = 16,
|
||||
QQSUBREG_0= 17, QQSUBREG_1= 18
|
||||
};
|
||||
}
|
||||
|
||||
struct ARMRegisterInfo : public ARMBaseRegisterInfo {
|
||||
public:
|
||||
ARMRegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI);
|
||||
|
||||
@ -445,29 +445,29 @@ def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]>;
|
||||
// Subregister Set Definitions... now that we have all of the pieces, define the
|
||||
// sub registers for each register.
|
||||
//
|
||||
let Namespace = "ARM" in {
|
||||
def ssub_0 : SubRegIndex { let NumberHack = 1; }
|
||||
def ssub_1 : SubRegIndex { let NumberHack = 2; }
|
||||
def ssub_2 : SubRegIndex { let NumberHack = 3; }
|
||||
def ssub_3 : SubRegIndex { let NumberHack = 4; }
|
||||
|
||||
def arm_ssubreg_0 : PatLeaf<(i32 1)>;
|
||||
def arm_ssubreg_1 : PatLeaf<(i32 2)>;
|
||||
def arm_ssubreg_2 : PatLeaf<(i32 3)>;
|
||||
def arm_ssubreg_3 : PatLeaf<(i32 4)>;
|
||||
def dsub_0 : SubRegIndex { let NumberHack = 5; }
|
||||
def dsub_1 : SubRegIndex { let NumberHack = 6; }
|
||||
def dsub_2 : SubRegIndex { let NumberHack = 7; }
|
||||
def dsub_3 : SubRegIndex { let NumberHack = 8; }
|
||||
def dsub_4 : SubRegIndex { let NumberHack = 9; }
|
||||
def dsub_5 : SubRegIndex { let NumberHack = 10; }
|
||||
def dsub_6 : SubRegIndex { let NumberHack = 11; }
|
||||
def dsub_7 : SubRegIndex { let NumberHack = 12; }
|
||||
|
||||
def arm_dsubreg_0 : PatLeaf<(i32 5)>;
|
||||
def arm_dsubreg_1 : PatLeaf<(i32 6)>;
|
||||
def arm_dsubreg_2 : PatLeaf<(i32 7)>;
|
||||
def arm_dsubreg_3 : PatLeaf<(i32 8)>;
|
||||
def arm_dsubreg_4 : PatLeaf<(i32 9)>;
|
||||
def arm_dsubreg_5 : PatLeaf<(i32 10)>;
|
||||
def arm_dsubreg_6 : PatLeaf<(i32 11)>;
|
||||
def arm_dsubreg_7 : PatLeaf<(i32 12)>;
|
||||
|
||||
def arm_qsubreg_0 : PatLeaf<(i32 13)>;
|
||||
def arm_qsubreg_1 : PatLeaf<(i32 14)>;
|
||||
def arm_qsubreg_2 : PatLeaf<(i32 15)>;
|
||||
def arm_qsubreg_3 : PatLeaf<(i32 16)>;
|
||||
|
||||
def arm_qqsubreg_0 : PatLeaf<(i32 17)>;
|
||||
def arm_qqsubreg_1 : PatLeaf<(i32 18)>;
|
||||
def qsub_0 : SubRegIndex { let NumberHack = 13; }
|
||||
def qsub_1 : SubRegIndex { let NumberHack = 14; }
|
||||
def qsub_2 : SubRegIndex { let NumberHack = 15; }
|
||||
def qsub_3 : SubRegIndex { let NumberHack = 16; }
|
||||
|
||||
def qqsub_0 : SubRegIndex { let NumberHack = 17; }
|
||||
def qqsub_1 : SubRegIndex { let NumberHack = 18; }
|
||||
}
|
||||
|
||||
// S sub-registers of D registers.
|
||||
def : SubRegSet<1, [D0, D1, D2, D3, D4, D5, D6, D7,
|
||||
|
||||
@ -319,8 +319,8 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
|
||||
unsigned Reg = MO.getReg();
|
||||
assert(TargetRegisterInfo::isPhysicalRegister(Reg));
|
||||
if (Modifier && strcmp(Modifier, "dregpair") == 0) {
|
||||
unsigned DRegLo = TM.getRegisterInfo()->getSubReg(Reg, 5);// arm_dsubreg_0
|
||||
unsigned DRegHi = TM.getRegisterInfo()->getSubReg(Reg, 6);// arm_dsubreg_1
|
||||
unsigned DRegLo = TM.getRegisterInfo()->getSubReg(Reg, ARM::dsub_0);
|
||||
unsigned DRegHi = TM.getRegisterInfo()->getSubReg(Reg, ARM::dsub_1);
|
||||
O << '{'
|
||||
<< getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi)
|
||||
<< '}';
|
||||
|
||||
@ -195,8 +195,8 @@ void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
|
||||
// FIXME: Breaks e.g. ARM/vmul.ll.
|
||||
assert(0);
|
||||
/*
|
||||
unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0
|
||||
unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1
|
||||
unsigned DRegLo = TRI->getSubReg(Reg, ARM::dsub_0);
|
||||
unsigned DRegHi = TRI->getSubReg(Reg, ARM::dsub_1);
|
||||
O << '{'
|
||||
<< getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi)
|
||||
<< '}';*/
|
||||
|
||||
@ -375,9 +375,9 @@ NEONPreAllocPass::FormsRegSequence(MachineInstr *MI,
|
||||
if (LastSubIdx != SubIdx-Stride)
|
||||
return false;
|
||||
} else {
|
||||
// Must start from arm_dsubreg_0 or arm_qsubreg_0.
|
||||
if (SubIdx != (ARM::DSUBREG_0+Offset) &&
|
||||
SubIdx != (ARM::QSUBREG_0+Offset))
|
||||
// Must start from dsub_0 or qsub_0.
|
||||
if (SubIdx != (ARM::dsub_0+Offset) &&
|
||||
SubIdx != (ARM::qsub_0+Offset))
|
||||
return false;
|
||||
}
|
||||
RegSeq = UseMI;
|
||||
@ -423,9 +423,9 @@ NEONPreAllocPass::FormsRegSequence(MachineInstr *MI,
|
||||
if (LastSubIdx != SubIdx-Stride)
|
||||
return false;
|
||||
} else {
|
||||
// Must start from arm_dsubreg_0 or arm_qsubreg_0.
|
||||
if (SubIdx != (ARM::DSUBREG_0+Offset) &&
|
||||
SubIdx != (ARM::QSUBREG_0+Offset))
|
||||
// Must start from dsub_0 or qsub_0.
|
||||
if (SubIdx != (ARM::dsub_0+Offset) &&
|
||||
SubIdx != (ARM::qsub_0+Offset))
|
||||
return false;
|
||||
}
|
||||
SubIds.push_back(SubIdx);
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user