mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-08-05 13:26:55 +00:00
x86 CPU detection and proper subtarget support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25679 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
@@ -33,6 +33,9 @@ static cl::opt<bool> EnableFastCC("enable-x86-fastcc", cl::Hidden,
|
||||
|
||||
X86TargetLowering::X86TargetLowering(TargetMachine &TM)
|
||||
: TargetLowering(TM) {
|
||||
Subtarget = &TM.getSubtarget<X86Subtarget>();
|
||||
X86ScalarSSE = Subtarget->hasSSE2();
|
||||
|
||||
// Set up the TargetLowering object.
|
||||
|
||||
// X86 is weird, it always uses i8 for shift amounts and setcc results.
|
||||
@@ -1657,8 +1660,8 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
|
||||
case ISD::SELECT: {
|
||||
MVT::ValueType VT = Op.getValueType();
|
||||
bool isFP = MVT::isFloatingPoint(VT);
|
||||
bool isFPStack = isFP && (X86Vector < SSE2);
|
||||
bool isFPSSE = isFP && (X86Vector >= SSE2);
|
||||
bool isFPStack = isFP && !X86ScalarSSE;
|
||||
bool isFPSSE = isFP && X86ScalarSSE;
|
||||
bool addTest = false;
|
||||
SDOperand Op0 = Op.getOperand(0);
|
||||
SDOperand Cond, CC;
|
||||
|
Reference in New Issue
Block a user