mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 04:30:12 +00:00
Make a bunch of lowering helper functions static instead of member functions. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163596 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
9e6dc8b9e7
commit
55b2405484
@ -5021,7 +5021,7 @@ static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
|
||||
/// The VBROADCAST node is returned when a pattern is found,
|
||||
/// or SDValue() otherwise.
|
||||
SDValue
|
||||
X86TargetLowering::LowerVectorBroadcast(SDValue &Op, SelectionDAG &DAG) const {
|
||||
X86TargetLowering::LowerVectorBroadcast(SDValue Op, SelectionDAG &DAG) const {
|
||||
if (!Subtarget->hasAVX())
|
||||
return SDValue();
|
||||
|
||||
@ -5571,8 +5571,7 @@ static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
|
||||
return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
|
||||
}
|
||||
|
||||
SDValue
|
||||
X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
|
||||
static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
|
||||
assert(Op.getNumOperands() == 2);
|
||||
|
||||
// 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
|
||||
@ -5581,9 +5580,9 @@ X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
|
||||
}
|
||||
|
||||
// Try to lower a shuffle node into a simple blend instruction.
|
||||
static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
|
||||
const X86Subtarget *Subtarget,
|
||||
SelectionDAG &DAG) {
|
||||
static SDValue
|
||||
LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
|
||||
const X86Subtarget *Subtarget, SelectionDAG &DAG) {
|
||||
SDValue V1 = SVOp->getOperand(0);
|
||||
SDValue V2 = SVOp->getOperand(1);
|
||||
DebugLoc dl = SVOp->getDebugLoc();
|
||||
@ -5653,9 +5652,9 @@ static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
|
||||
// 2. [ssse3] 1 x pshufb
|
||||
// 3. [ssse3] 2 x pshufb + 1 x por
|
||||
// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
|
||||
SDValue
|
||||
X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
|
||||
SelectionDAG &DAG) const {
|
||||
static SDValue
|
||||
LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
|
||||
SelectionDAG &DAG) {
|
||||
ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
|
||||
SDValue V1 = SVOp->getOperand(0);
|
||||
SDValue V2 = SVOp->getOperand(1);
|
||||
@ -6028,8 +6027,8 @@ SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
|
||||
// v32i8 shuffles - Translate to VPSHUFB if possible.
|
||||
static
|
||||
SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
|
||||
SelectionDAG &DAG,
|
||||
const X86TargetLowering &TLI) {
|
||||
const X86Subtarget *Subtarget,
|
||||
SelectionDAG &DAG) {
|
||||
EVT VT = SVOp->getValueType(0);
|
||||
SDValue V1 = SVOp->getOperand(0);
|
||||
SDValue V2 = SVOp->getOperand(1);
|
||||
@ -6044,7 +6043,7 @@ SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
|
||||
// (1) one of input vector is undefined or zeroinitializer.
|
||||
// The mask value 0x80 puts 0 in the corresponding slot of the vector.
|
||||
// And (2) the mask indexes don't cross the 128-bit lane.
|
||||
if (VT != MVT::v32i8 || !TLI.getSubtarget()->hasAVX2() ||
|
||||
if (VT != MVT::v32i8 || !Subtarget->hasAVX2() ||
|
||||
(!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
|
||||
return SDValue();
|
||||
|
||||
@ -6885,7 +6884,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
|
||||
|
||||
// Handle v8i16 specifically since SSE can do byte extraction and insertion.
|
||||
if (VT == MVT::v8i16) {
|
||||
SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
|
||||
SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
|
||||
if (NewOp.getNode())
|
||||
return NewOp;
|
||||
}
|
||||
@ -6897,7 +6896,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
|
||||
}
|
||||
|
||||
if (VT == MVT::v32i8) {
|
||||
SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, DAG, *this);
|
||||
SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
|
||||
if (NewOp.getNode())
|
||||
return NewOp;
|
||||
}
|
||||
@ -7173,8 +7172,7 @@ X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
|
||||
return SDValue();
|
||||
}
|
||||
|
||||
SDValue
|
||||
X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
|
||||
static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
|
||||
LLVMContext *Context = DAG.getContext();
|
||||
DebugLoc dl = Op.getDebugLoc();
|
||||
EVT OpVT = Op.getValueType();
|
||||
@ -7206,8 +7204,8 @@ X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
|
||||
// Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
|
||||
// a simple subregister reference or explicit instructions to grab
|
||||
// upper bits of a vector.
|
||||
SDValue
|
||||
X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
|
||||
static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
|
||||
SelectionDAG &DAG) {
|
||||
if (Subtarget->hasAVX()) {
|
||||
DebugLoc dl = Op.getNode()->getDebugLoc();
|
||||
SDValue Vec = Op.getNode()->getOperand(0);
|
||||
@ -7226,8 +7224,8 @@ X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
|
||||
// Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
|
||||
// simple superregister reference or explicit instructions to insert
|
||||
// the upper bits of a vector.
|
||||
SDValue
|
||||
X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
|
||||
static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
|
||||
SelectionDAG &DAG) {
|
||||
if (Subtarget->hasAVX()) {
|
||||
DebugLoc dl = Op.getNode()->getDebugLoc();
|
||||
SDValue Vec = Op.getNode()->getOperand(0);
|
||||
@ -8337,7 +8335,7 @@ SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
|
||||
return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
|
||||
}
|
||||
|
||||
SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
|
||||
static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
|
||||
SDValue N0 = Op.getOperand(0);
|
||||
DebugLoc dl = Op.getDebugLoc();
|
||||
EVT VT = Op.getValueType();
|
||||
@ -9587,7 +9585,8 @@ SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
|
||||
false, false, false, 0);
|
||||
}
|
||||
|
||||
SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
|
||||
static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
|
||||
SelectionDAG &DAG) {
|
||||
// X86-64 va_list is a struct { i32, i32, i8*, i8* }.
|
||||
assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
|
||||
SDValue Chain = Op.getOperand(0);
|
||||
@ -9648,8 +9647,7 @@ static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT,
|
||||
return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
|
||||
}
|
||||
|
||||
SDValue
|
||||
X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
|
||||
static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
|
||||
DebugLoc dl = Op.getDebugLoc();
|
||||
unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
|
||||
switch (IntNo) {
|
||||
@ -10186,8 +10184,7 @@ X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
|
||||
}
|
||||
}
|
||||
|
||||
SDValue
|
||||
X86TargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const {
|
||||
static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) {
|
||||
DebugLoc dl = Op.getDebugLoc();
|
||||
unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
|
||||
switch (IntNo) {
|
||||
@ -10287,8 +10284,7 @@ SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
|
||||
Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
|
||||
}
|
||||
|
||||
SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
|
||||
SelectionDAG &DAG) const {
|
||||
static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
|
||||
return Op.getOperand(0);
|
||||
}
|
||||
|
||||
@ -10511,7 +10507,7 @@ SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
|
||||
ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
|
||||
}
|
||||
|
||||
SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
|
||||
static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
|
||||
EVT VT = Op.getValueType();
|
||||
EVT OpVT = VT;
|
||||
unsigned NumBits = VT.getSizeInBits();
|
||||
@ -10545,8 +10541,7 @@ SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
|
||||
return Op;
|
||||
}
|
||||
|
||||
SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op,
|
||||
SelectionDAG &DAG) const {
|
||||
static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
|
||||
EVT VT = Op.getValueType();
|
||||
EVT OpVT = VT;
|
||||
unsigned NumBits = VT.getSizeInBits();
|
||||
@ -10571,7 +10566,7 @@ SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op,
|
||||
return Op;
|
||||
}
|
||||
|
||||
SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
|
||||
static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
|
||||
EVT VT = Op.getValueType();
|
||||
unsigned NumBits = VT.getSizeInBits();
|
||||
DebugLoc dl = Op.getDebugLoc();
|
||||
@ -10620,21 +10615,22 @@ static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
|
||||
DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
|
||||
}
|
||||
|
||||
SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
|
||||
static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
|
||||
assert(Op.getValueType().is256BitVector() &&
|
||||
Op.getValueType().isInteger() &&
|
||||
"Only handle AVX 256-bit vector integer operation");
|
||||
return Lower256IntArith(Op, DAG);
|
||||
}
|
||||
|
||||
SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
|
||||
static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
|
||||
assert(Op.getValueType().is256BitVector() &&
|
||||
Op.getValueType().isInteger() &&
|
||||
"Only handle AVX 256-bit vector integer operation");
|
||||
return Lower256IntArith(Op, DAG);
|
||||
}
|
||||
|
||||
SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
|
||||
static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
|
||||
SelectionDAG &DAG) {
|
||||
EVT VT = Op.getValueType();
|
||||
|
||||
// Decompose 256-bit ops into smaller 128-bit ops.
|
||||
@ -10909,7 +10905,7 @@ SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
|
||||
return SDValue();
|
||||
}
|
||||
|
||||
SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
|
||||
static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
|
||||
// Lower the "add/sub/mul with overflow" instruction into a regular ins plus
|
||||
// a "setcc" instruction that checks the overflow flag. The "brcond" lowering
|
||||
// looks for this combo and may remove the "setcc" instruction if the "setcc"
|
||||
@ -11037,7 +11033,8 @@ SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
|
||||
}
|
||||
|
||||
|
||||
SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
|
||||
static SDValue LowerMEMBARRIER(SDValue Op, const X86Subtarget *Subtarget,
|
||||
SelectionDAG &DAG) {
|
||||
DebugLoc dl = Op.getDebugLoc();
|
||||
|
||||
// Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
|
||||
@ -11082,8 +11079,8 @@ SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
|
||||
return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
|
||||
}
|
||||
|
||||
SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
|
||||
SelectionDAG &DAG) const {
|
||||
static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
|
||||
SelectionDAG &DAG) {
|
||||
DebugLoc dl = Op.getDebugLoc();
|
||||
AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
|
||||
cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
|
||||
@ -11121,7 +11118,8 @@ SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
|
||||
}
|
||||
|
||||
|
||||
SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
|
||||
static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
|
||||
SelectionDAG &DAG) {
|
||||
EVT T = Op.getValueType();
|
||||
DebugLoc DL = Op.getDebugLoc();
|
||||
unsigned Reg = 0;
|
||||
@ -11152,8 +11150,8 @@ SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
|
||||
return cpOut;
|
||||
}
|
||||
|
||||
SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
|
||||
SelectionDAG &DAG) const {
|
||||
static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
|
||||
SelectionDAG &DAG) {
|
||||
assert(Subtarget->is64Bit() && "Result not type legalized?");
|
||||
SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
|
||||
SDValue TheChain = Op.getOperand(0);
|
||||
@ -11171,8 +11169,7 @@ SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
|
||||
return DAG.getMergeValues(Ops, 2, dl);
|
||||
}
|
||||
|
||||
SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
|
||||
SelectionDAG &DAG) const {
|
||||
SDValue X86TargetLowering::LowerBITCAST(SDValue Op, SelectionDAG &DAG) const {
|
||||
EVT SrcVT = Op.getOperand(0).getValueType();
|
||||
EVT DstVT = Op.getValueType();
|
||||
assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
|
||||
@ -11192,7 +11189,7 @@ SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
|
||||
return SDValue();
|
||||
}
|
||||
|
||||
SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
|
||||
static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
|
||||
SDNode *Node = Op.getNode();
|
||||
DebugLoc dl = Node->getDebugLoc();
|
||||
EVT T = Node->getValueType(0);
|
||||
@ -11265,9 +11262,9 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
|
||||
switch (Op.getOpcode()) {
|
||||
default: llvm_unreachable("Should not custom lower this!");
|
||||
case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
|
||||
case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
|
||||
case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
|
||||
case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
|
||||
case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, Subtarget, DAG);
|
||||
case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
|
||||
case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op, Subtarget, DAG);
|
||||
case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
|
||||
case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
|
||||
case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
|
||||
@ -11275,8 +11272,8 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
|
||||
case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
|
||||
case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
|
||||
case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
|
||||
case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
|
||||
case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
|
||||
case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
|
||||
case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
|
||||
case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
|
||||
case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
|
||||
case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
|
||||
@ -11300,7 +11297,7 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
|
||||
case ISD::JumpTable: return LowerJumpTable(Op, DAG);
|
||||
case ISD::VASTART: return LowerVASTART(Op, DAG);
|
||||
case ISD::VAARG: return LowerVAARG(Op, DAG);
|
||||
case ISD::VACOPY: return LowerVACOPY(Op, DAG);
|
||||
case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
|
||||
case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
|
||||
case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
|
||||
case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
|
||||
@ -11315,7 +11312,7 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
|
||||
case ISD::CTLZ: return LowerCTLZ(Op, DAG);
|
||||
case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
|
||||
case ISD::CTTZ: return LowerCTTZ(Op, DAG);
|
||||
case ISD::MUL: return LowerMUL(Op, DAG);
|
||||
case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
|
||||
case ISD::SRA:
|
||||
case ISD::SRL:
|
||||
case ISD::SHL: return LowerShift(Op, DAG);
|
||||
@ -11325,7 +11322,7 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
|
||||
case ISD::USUBO:
|
||||
case ISD::SMULO:
|
||||
case ISD::UMULO: return LowerXALUO(Op, DAG);
|
||||
case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
|
||||
case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
|
||||
case ISD::BITCAST: return LowerBITCAST(Op, DAG);
|
||||
case ISD::ADDC:
|
||||
case ISD::ADDE:
|
||||
@ -13498,12 +13495,12 @@ static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
|
||||
}
|
||||
|
||||
|
||||
/// DCI, PerformTruncateCombine - Converts truncate operation to
|
||||
/// PerformTruncateCombine - Converts truncate operation to
|
||||
/// a sequence of vector shuffle operations.
|
||||
/// It is possible when we truncate 256-bit vector to 128-bit vector
|
||||
|
||||
SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
|
||||
DAGCombinerInfo &DCI) const {
|
||||
static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
|
||||
TargetLowering::DAGCombinerInfo &DCI,
|
||||
const X86Subtarget *Subtarget) {
|
||||
if (!DCI.isBeforeLegalizeOps())
|
||||
return SDValue();
|
||||
|
||||
@ -16114,7 +16111,7 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
|
||||
case ISD::ANY_EXTEND:
|
||||
case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
|
||||
case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
|
||||
case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG, DCI);
|
||||
case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
|
||||
case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
|
||||
case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
|
||||
case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
|
||||
|
||||
@ -763,15 +763,11 @@ namespace llvm {
|
||||
SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
|
||||
SelectionDAG &DAG) const;
|
||||
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
|
||||
@ -790,7 +786,6 @@ namespace llvm {
|
||||
SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerToBT(SDValue And, ISD::CondCode CC,
|
||||
DebugLoc dl, SelectionDAG &DAG) const;
|
||||
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
|
||||
@ -802,36 +797,18 @@ namespace llvm {
|
||||
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerADD(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
|
||||
|
||||
SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue PerformTruncateCombine(SDNode* N, SelectionDAG &DAG, DAGCombinerInfo &DCI) const;
|
||||
|
||||
// Utility functions to help LowerVECTOR_SHUFFLE
|
||||
SDValue LowerVECTOR_SHUFFLEv8i16(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerVectorBroadcast(SDValue &Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerVectorBroadcast(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const;
|
||||
|
||||
SDValue LowerVectorFpExtend(SDValue &Op, SelectionDAG &DAG) const;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user