mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Misc optimizer+codegen work for 'cmpxchg' and 'atomicrmw'. They appear to be
working on x86 (at least for trivial testcases); other architectures will need more work so that they actually emit the appropriate instructions for orderings stricter than 'monotonic'. (As far as I can tell, the ARM, PPC, Mips, and Alpha backends need such changes.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136457 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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@ -342,6 +342,10 @@ public:
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case Instruction::Load: return getModRefInfo((const LoadInst*)I, Loc);
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case Instruction::Load: return getModRefInfo((const LoadInst*)I, Loc);
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case Instruction::Store: return getModRefInfo((const StoreInst*)I, Loc);
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case Instruction::Store: return getModRefInfo((const StoreInst*)I, Loc);
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case Instruction::Fence: return getModRefInfo((const FenceInst*)I, Loc);
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case Instruction::Fence: return getModRefInfo((const FenceInst*)I, Loc);
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case Instruction::AtomicCmpXchg:
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return getModRefInfo((const AtomicCmpXchgInst*)I, Loc);
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case Instruction::AtomicRMW:
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return getModRefInfo((const AtomicRMWInst*)I, Loc);
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case Instruction::Call: return getModRefInfo((const CallInst*)I, Loc);
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case Instruction::Call: return getModRefInfo((const CallInst*)I, Loc);
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case Instruction::Invoke: return getModRefInfo((const InvokeInst*)I,Loc);
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case Instruction::Invoke: return getModRefInfo((const InvokeInst*)I,Loc);
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default: return NoModRef;
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default: return NoModRef;
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@ -420,6 +424,32 @@ public:
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return getModRefInfo(S, Location(P, Size));
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return getModRefInfo(S, Location(P, Size));
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}
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}
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/// getModRefInfo (for cmpxchges) - Return whether information about whether
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/// a particular cmpxchg modifies or reads the specified memory location.
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ModRefResult getModRefInfo(const AtomicCmpXchgInst *CX, const Location &Loc) {
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// Conservatively correct. (But there are obvious ways to be smarter.)
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return ModRef;
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}
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/// getModRefInfo (for cmpxchges) - A convenience wrapper.
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ModRefResult getModRefInfo(const AtomicCmpXchgInst *CX,
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const Value *P, unsigned Size) {
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return getModRefInfo(CX, Location(P, Size));
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}
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/// getModRefInfo (for atomicrmws) - Return whether information about whether
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/// a particular atomicrmw modifies or reads the specified memory location.
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ModRefResult getModRefInfo(const AtomicRMWInst *RMW, const Location &Loc) {
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// Conservatively correct. (But there are obvious ways to be smarter.)
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return ModRef;
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}
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/// getModRefInfo (for atomicrmws) - A convenience wrapper.
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ModRefResult getModRefInfo(const AtomicRMWInst *RMW,
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const Value *P, unsigned Size) {
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return getModRefInfo(RMW, Location(P, Size));
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}
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/// getModRefInfo (for va_args) - Return whether information about whether
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/// getModRefInfo (for va_args) - Return whether information about whether
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/// a particular va_arg modifies or reads the specified memory location.
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/// a particular va_arg modifies or reads the specified memory location.
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ModRefResult getModRefInfo(const VAArgInst* I, const Location &Loc);
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ModRefResult getModRefInfo(const VAArgInst* I, const Location &Loc);
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@ -589,19 +589,27 @@ public:
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/// takes 3 operands
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/// takes 3 operands
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SDValue getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, SDValue Chain,
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SDValue getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, SDValue Chain,
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SDValue Ptr, SDValue Cmp, SDValue Swp,
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SDValue Ptr, SDValue Cmp, SDValue Swp,
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MachinePointerInfo PtrInfo, unsigned Alignment=0);
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MachinePointerInfo PtrInfo, unsigned Alignment,
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AtomicOrdering Ordering,
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SynchronizationScope SynchScope);
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SDValue getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, SDValue Chain,
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SDValue getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, SDValue Chain,
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SDValue Ptr, SDValue Cmp, SDValue Swp,
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SDValue Ptr, SDValue Cmp, SDValue Swp,
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MachineMemOperand *MMO);
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MachineMemOperand *MMO,
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AtomicOrdering Ordering,
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SynchronizationScope SynchScope);
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/// getAtomic - Gets a node for an atomic op, produces result and chain and
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/// getAtomic - Gets a node for an atomic op, produces result and chain and
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/// takes 2 operands.
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/// takes 2 operands.
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SDValue getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, SDValue Chain,
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SDValue getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, SDValue Chain,
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SDValue Ptr, SDValue Val, const Value* PtrVal,
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SDValue Ptr, SDValue Val, const Value* PtrVal,
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unsigned Alignment = 0);
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unsigned Alignment,
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AtomicOrdering Ordering,
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SynchronizationScope SynchScope);
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SDValue getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, SDValue Chain,
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SDValue getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, SDValue Chain,
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SDValue Ptr, SDValue Val,
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SDValue Ptr, SDValue Val,
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MachineMemOperand *MMO);
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MachineMemOperand *MMO,
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AtomicOrdering Ordering,
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SynchronizationScope SynchScope);
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/// getMemIntrinsicNode - Creates a MemIntrinsicNode that may produce a
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/// getMemIntrinsicNode - Creates a MemIntrinsicNode that may produce a
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/// result and takes a list of operands. Opcode may be INTRINSIC_VOID,
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/// result and takes a list of operands. Opcode may be INTRINSIC_VOID,
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@ -20,6 +20,7 @@
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#define LLVM_CODEGEN_SELECTIONDAGNODES_H
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#define LLVM_CODEGEN_SELECTIONDAGNODES_H
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#include "llvm/Constants.h"
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#include "llvm/Constants.h"
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#include "llvm/Instructions.h"
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#include "llvm/ADT/FoldingSet.h"
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#include "llvm/ADT/FoldingSet.h"
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#include "llvm/ADT/GraphTraits.h"
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#include "llvm/ADT/GraphTraits.h"
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#include "llvm/ADT/ilist_node.h"
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#include "llvm/ADT/ilist_node.h"
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@ -917,6 +918,13 @@ public:
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bool isVolatile() const { return (SubclassData >> 5) & 1; }
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bool isVolatile() const { return (SubclassData >> 5) & 1; }
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bool isNonTemporal() const { return (SubclassData >> 6) & 1; }
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bool isNonTemporal() const { return (SubclassData >> 6) & 1; }
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AtomicOrdering getOrdering() const {
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return AtomicOrdering((SubclassData >> 7) & 15);
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}
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SynchronizationScope getSynchScope() const {
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return SynchronizationScope((SubclassData >> 11) & 1);
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}
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/// Returns the SrcValue and offset that describes the location of the access
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/// Returns the SrcValue and offset that describes the location of the access
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const Value *getSrcValue() const { return MMO->getValue(); }
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const Value *getSrcValue() const { return MMO->getValue(); }
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int64_t getSrcValueOffset() const { return MMO->getOffset(); }
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int64_t getSrcValueOffset() const { return MMO->getOffset(); }
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@ -977,6 +985,21 @@ public:
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class AtomicSDNode : public MemSDNode {
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class AtomicSDNode : public MemSDNode {
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SDUse Ops[4];
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SDUse Ops[4];
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void InitAtomic(AtomicOrdering Ordering, SynchronizationScope SynchScope) {
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// This must match encodeMemSDNodeFlags() in SelectionDAG.cpp.
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assert((Ordering & 15) == Ordering &&
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"Ordering may not require more than 4 bits!");
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assert((SynchScope & 1) == SynchScope &&
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"SynchScope may not require more than 1 bit!");
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SubclassData |= Ordering << 7;
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SubclassData |= SynchScope << 11;
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assert(getOrdering() == Ordering && "Ordering encoding error!");
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assert(getSynchScope() == SynchScope && "Synch-scope encoding error!");
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assert(readMem() && "Atomic MachineMemOperand is not a load!");
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assert(writeMem() && "Atomic MachineMemOperand is not a store!");
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}
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public:
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public:
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// Opc: opcode for atomic
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// Opc: opcode for atomic
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// VTL: value type list
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// VTL: value type list
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@ -988,18 +1011,18 @@ public:
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// Align: alignment of memory
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// Align: alignment of memory
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AtomicSDNode(unsigned Opc, DebugLoc dl, SDVTList VTL, EVT MemVT,
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AtomicSDNode(unsigned Opc, DebugLoc dl, SDVTList VTL, EVT MemVT,
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SDValue Chain, SDValue Ptr,
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SDValue Chain, SDValue Ptr,
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SDValue Cmp, SDValue Swp, MachineMemOperand *MMO)
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SDValue Cmp, SDValue Swp, MachineMemOperand *MMO,
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AtomicOrdering Ordering, SynchronizationScope SynchScope)
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: MemSDNode(Opc, dl, VTL, MemVT, MMO) {
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: MemSDNode(Opc, dl, VTL, MemVT, MMO) {
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assert(readMem() && "Atomic MachineMemOperand is not a load!");
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InitAtomic(Ordering, SynchScope);
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assert(writeMem() && "Atomic MachineMemOperand is not a store!");
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InitOperands(Ops, Chain, Ptr, Cmp, Swp);
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InitOperands(Ops, Chain, Ptr, Cmp, Swp);
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}
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}
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AtomicSDNode(unsigned Opc, DebugLoc dl, SDVTList VTL, EVT MemVT,
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AtomicSDNode(unsigned Opc, DebugLoc dl, SDVTList VTL, EVT MemVT,
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SDValue Chain, SDValue Ptr,
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SDValue Chain, SDValue Ptr,
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SDValue Val, MachineMemOperand *MMO)
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SDValue Val, MachineMemOperand *MMO,
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AtomicOrdering Ordering, SynchronizationScope SynchScope)
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: MemSDNode(Opc, dl, VTL, MemVT, MMO) {
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: MemSDNode(Opc, dl, VTL, MemVT, MMO) {
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assert(readMem() && "Atomic MachineMemOperand is not a load!");
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InitAtomic(Ordering, SynchScope);
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assert(writeMem() && "Atomic MachineMemOperand is not a store!");
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InitOperands(Ops, Chain, Ptr, Val);
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InitOperands(Ops, Chain, Ptr, Val);
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}
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}
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@ -770,6 +770,16 @@ public:
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SynchronizationScope SynchScope = CrossThread) {
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SynchronizationScope SynchScope = CrossThread) {
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return Insert(new FenceInst(Context, Ordering, SynchScope));
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return Insert(new FenceInst(Context, Ordering, SynchScope));
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}
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}
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FenceInst *CreateAtomicCmpXchg(Value *Ptr, Value *Cmp, Value *New,
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AtomicOrdering Ordering,
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SynchronizationScope SynchScope = CrossThread){
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return Insert(new AtomicCmpXchgInst(Ptr, Cmp, New, Ordering, SynchScope));
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}
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FenceInst *CreateAtomicRMW(AtomicRMWInst::BinOp Op, Value *Ptr, Value *Val,
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AtomicOrdering Ordering,
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SynchronizationScope SynchScope = CrossThread) {
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return Insert(new AtomicRMWInst(Op, Ptr, Val, Ordering, SynchScope));
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}
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Value *CreateGEP(Value *Ptr, ArrayRef<Value *> IdxList,
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Value *CreateGEP(Value *Ptr, ArrayRef<Value *> IdxList,
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const Twine &Name = "") {
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const Twine &Name = "") {
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if (Constant *PC = dyn_cast<Constant>(Ptr)) {
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if (Constant *PC = dyn_cast<Constant>(Ptr)) {
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@ -155,7 +155,8 @@ SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
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SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
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SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
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N->getMemoryVT(),
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N->getMemoryVT(),
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N->getChain(), N->getBasePtr(),
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N->getChain(), N->getBasePtr(),
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Op2, N->getMemOperand());
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Op2, N->getMemOperand(), N->getOrdering(),
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N->getSynchScope());
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// Legalized the chain result - switch anything that used the old chain to
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// Legalized the chain result - switch anything that used the old chain to
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// use the new one.
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// use the new one.
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ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
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ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
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@ -167,7 +168,8 @@ SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) {
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SDValue Op3 = GetPromotedInteger(N->getOperand(3));
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SDValue Op3 = GetPromotedInteger(N->getOperand(3));
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SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
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SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
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N->getMemoryVT(), N->getChain(), N->getBasePtr(),
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N->getMemoryVT(), N->getChain(), N->getBasePtr(),
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Op2, Op3, N->getMemOperand());
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Op2, Op3, N->getMemOperand(), N->getOrdering(),
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N->getSynchScope());
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// Legalized the chain result - switch anything that used the old chain to
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// Legalized the chain result - switch anything that used the old chain to
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// use the new one.
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// use the new one.
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ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
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ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
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@ -3815,7 +3815,9 @@ SDValue SelectionDAG::getMemset(SDValue Chain, DebugLoc dl, SDValue Dst,
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SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT,
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SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT,
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SDValue Chain, SDValue Ptr, SDValue Cmp,
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SDValue Chain, SDValue Ptr, SDValue Cmp,
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SDValue Swp, MachinePointerInfo PtrInfo,
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SDValue Swp, MachinePointerInfo PtrInfo,
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unsigned Alignment) {
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unsigned Alignment,
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AtomicOrdering Ordering,
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SynchronizationScope SynchScope) {
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if (Alignment == 0) // Ensure that codegen never sees alignment 0
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if (Alignment == 0) // Ensure that codegen never sees alignment 0
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Alignment = getEVTAlignment(MemVT);
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Alignment = getEVTAlignment(MemVT);
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@ -3828,13 +3830,16 @@ SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT,
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MachineMemOperand *MMO =
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MachineMemOperand *MMO =
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MF.getMachineMemOperand(PtrInfo, Flags, MemVT.getStoreSize(), Alignment);
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MF.getMachineMemOperand(PtrInfo, Flags, MemVT.getStoreSize(), Alignment);
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return getAtomic(Opcode, dl, MemVT, Chain, Ptr, Cmp, Swp, MMO);
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return getAtomic(Opcode, dl, MemVT, Chain, Ptr, Cmp, Swp, MMO,
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Ordering, SynchScope);
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}
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}
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SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT,
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SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT,
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SDValue Chain,
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SDValue Chain,
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SDValue Ptr, SDValue Cmp,
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SDValue Ptr, SDValue Cmp,
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SDValue Swp, MachineMemOperand *MMO) {
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SDValue Swp, MachineMemOperand *MMO,
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AtomicOrdering Ordering,
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SynchronizationScope SynchScope) {
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assert(Opcode == ISD::ATOMIC_CMP_SWAP && "Invalid Atomic Op");
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assert(Opcode == ISD::ATOMIC_CMP_SWAP && "Invalid Atomic Op");
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assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types");
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assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types");
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@ -3851,7 +3856,8 @@ SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT,
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return SDValue(E, 0);
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return SDValue(E, 0);
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}
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}
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SDNode *N = new (NodeAllocator) AtomicSDNode(Opcode, dl, VTs, MemVT, Chain,
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SDNode *N = new (NodeAllocator) AtomicSDNode(Opcode, dl, VTs, MemVT, Chain,
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Ptr, Cmp, Swp, MMO);
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Ptr, Cmp, Swp, MMO, Ordering,
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SynchScope);
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CSEMap.InsertNode(N, IP);
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CSEMap.InsertNode(N, IP);
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AllNodes.push_back(N);
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AllNodes.push_back(N);
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return SDValue(N, 0);
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return SDValue(N, 0);
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@ -3861,7 +3867,9 @@ SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT,
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SDValue Chain,
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SDValue Chain,
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SDValue Ptr, SDValue Val,
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SDValue Ptr, SDValue Val,
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const Value* PtrVal,
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const Value* PtrVal,
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unsigned Alignment) {
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unsigned Alignment,
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AtomicOrdering Ordering,
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SynchronizationScope SynchScope) {
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if (Alignment == 0) // Ensure that codegen never sees alignment 0
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if (Alignment == 0) // Ensure that codegen never sees alignment 0
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Alignment = getEVTAlignment(MemVT);
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Alignment = getEVTAlignment(MemVT);
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@ -3875,13 +3883,16 @@ SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT,
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MF.getMachineMemOperand(MachinePointerInfo(PtrVal), Flags,
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MF.getMachineMemOperand(MachinePointerInfo(PtrVal), Flags,
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MemVT.getStoreSize(), Alignment);
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MemVT.getStoreSize(), Alignment);
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return getAtomic(Opcode, dl, MemVT, Chain, Ptr, Val, MMO);
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return getAtomic(Opcode, dl, MemVT, Chain, Ptr, Val, MMO,
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Ordering, SynchScope);
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}
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}
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SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT,
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SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT,
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SDValue Chain,
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SDValue Chain,
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SDValue Ptr, SDValue Val,
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SDValue Ptr, SDValue Val,
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MachineMemOperand *MMO) {
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MachineMemOperand *MMO,
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AtomicOrdering Ordering,
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SynchronizationScope SynchScope) {
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assert((Opcode == ISD::ATOMIC_LOAD_ADD ||
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assert((Opcode == ISD::ATOMIC_LOAD_ADD ||
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Opcode == ISD::ATOMIC_LOAD_SUB ||
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Opcode == ISD::ATOMIC_LOAD_SUB ||
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Opcode == ISD::ATOMIC_LOAD_AND ||
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Opcode == ISD::ATOMIC_LOAD_AND ||
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@ -3908,7 +3919,8 @@ SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT,
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return SDValue(E, 0);
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return SDValue(E, 0);
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}
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}
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SDNode *N = new (NodeAllocator) AtomicSDNode(Opcode, dl, VTs, MemVT, Chain,
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SDNode *N = new (NodeAllocator) AtomicSDNode(Opcode, dl, VTs, MemVT, Chain,
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Ptr, Val, MMO);
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Ptr, Val, MMO,
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Ordering, SynchScope);
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CSEMap.InsertNode(N, IP);
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CSEMap.InsertNode(N, IP);
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AllNodes.push_back(N);
|
AllNodes.push_back(N);
|
||||||
return SDValue(N, 0);
|
return SDValue(N, 0);
|
||||||
|
@ -3257,9 +3257,46 @@ void SelectionDAGBuilder::visitStore(const StoreInst &I) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
|
void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
|
||||||
|
SDValue Root = getRoot();
|
||||||
|
SDValue L =
|
||||||
|
DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
|
||||||
|
getValue(I.getCompareOperand()).getValueType().getSimpleVT(),
|
||||||
|
Root,
|
||||||
|
getValue(I.getPointerOperand()),
|
||||||
|
getValue(I.getCompareOperand()),
|
||||||
|
getValue(I.getNewValOperand()),
|
||||||
|
MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */,
|
||||||
|
I.getOrdering(), I.getSynchScope());
|
||||||
|
setValue(&I, L);
|
||||||
|
DAG.setRoot(L.getValue(1));
|
||||||
}
|
}
|
||||||
|
|
||||||
void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
|
void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
|
||||||
|
ISD::NodeType NT;
|
||||||
|
switch (I.getOperation()) {
|
||||||
|
default: llvm_unreachable("Unknown atomicrmw operation"); return;
|
||||||
|
case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
|
||||||
|
case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
|
||||||
|
case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
|
||||||
|
case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
|
||||||
|
case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
|
||||||
|
case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
|
||||||
|
case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
|
||||||
|
case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
|
||||||
|
case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
|
||||||
|
case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
|
||||||
|
case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
|
||||||
|
}
|
||||||
|
SDValue L =
|
||||||
|
DAG.getAtomic(NT, getCurDebugLoc(),
|
||||||
|
getValue(I.getValOperand()).getValueType().getSimpleVT(),
|
||||||
|
getRoot(),
|
||||||
|
getValue(I.getPointerOperand()),
|
||||||
|
getValue(I.getValOperand()),
|
||||||
|
I.getPointerOperand(), 0 /* Alignment */,
|
||||||
|
I.getOrdering(), I.getSynchScope());
|
||||||
|
setValue(&I, L);
|
||||||
|
DAG.setRoot(L.getValue(1));
|
||||||
}
|
}
|
||||||
|
|
||||||
void SelectionDAGBuilder::visitFence(const FenceInst &I) {
|
void SelectionDAGBuilder::visitFence(const FenceInst &I) {
|
||||||
@ -3410,7 +3447,8 @@ SelectionDAGBuilder::implVisitBinaryAtomic(const CallInst& I,
|
|||||||
Root,
|
Root,
|
||||||
getValue(I.getArgOperand(0)),
|
getValue(I.getArgOperand(0)),
|
||||||
getValue(I.getArgOperand(1)),
|
getValue(I.getArgOperand(1)),
|
||||||
I.getArgOperand(0));
|
I.getArgOperand(0), 0 /* Alignment */,
|
||||||
|
Monotonic, CrossThread);
|
||||||
setValue(&I, L);
|
setValue(&I, L);
|
||||||
DAG.setRoot(L.getValue(1));
|
DAG.setRoot(L.getValue(1));
|
||||||
return 0;
|
return 0;
|
||||||
@ -4935,7 +4973,8 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
|
|||||||
getValue(I.getArgOperand(0)),
|
getValue(I.getArgOperand(0)),
|
||||||
getValue(I.getArgOperand(1)),
|
getValue(I.getArgOperand(1)),
|
||||||
getValue(I.getArgOperand(2)),
|
getValue(I.getArgOperand(2)),
|
||||||
MachinePointerInfo(I.getArgOperand(0)));
|
MachinePointerInfo(I.getArgOperand(0)), 0 /* Alignment */,
|
||||||
|
Monotonic, CrossThread);
|
||||||
setValue(&I, L);
|
setValue(&I, L);
|
||||||
DAG.setRoot(L.getValue(1));
|
DAG.setRoot(L.getValue(1));
|
||||||
return 0;
|
return 0;
|
||||||
|
@ -9562,7 +9562,9 @@ SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
|
|||||||
Node->getOperand(0),
|
Node->getOperand(0),
|
||||||
Node->getOperand(1), negOp,
|
Node->getOperand(1), negOp,
|
||||||
cast<AtomicSDNode>(Node)->getSrcValue(),
|
cast<AtomicSDNode>(Node)->getSrcValue(),
|
||||||
cast<AtomicSDNode>(Node)->getAlignment());
|
cast<AtomicSDNode>(Node)->getAlignment(),
|
||||||
|
cast<AtomicSDNode>(Node)->getOrdering(),
|
||||||
|
cast<AtomicSDNode>(Node)->getSynchScope());
|
||||||
}
|
}
|
||||||
|
|
||||||
static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
|
static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
|
||||||
|
@ -317,22 +317,22 @@ bool FunctionComparator::isEquivalentOperation(const Instruction *I1,
|
|||||||
if (const InvokeInst *CI = dyn_cast<InvokeInst>(I1))
|
if (const InvokeInst *CI = dyn_cast<InvokeInst>(I1))
|
||||||
return CI->getCallingConv() == cast<InvokeInst>(I2)->getCallingConv() &&
|
return CI->getCallingConv() == cast<InvokeInst>(I2)->getCallingConv() &&
|
||||||
CI->getAttributes() == cast<InvokeInst>(I2)->getAttributes();
|
CI->getAttributes() == cast<InvokeInst>(I2)->getAttributes();
|
||||||
if (const InsertValueInst *IVI = dyn_cast<InsertValueInst>(I1)) {
|
if (const InsertValueInst *IVI = dyn_cast<InsertValueInst>(I1))
|
||||||
if (IVI->getNumIndices() != cast<InsertValueInst>(I2)->getNumIndices())
|
return IVI->getIndices() == cast<InsertValueInst>(I2)->getIndices();
|
||||||
return false;
|
if (const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(I1))
|
||||||
for (unsigned i = 0, e = IVI->getNumIndices(); i != e; ++i)
|
return EVI->getIndices() == cast<ExtractValueInst>(I2)->getIndices();
|
||||||
if (IVI->idx_begin()[i] != cast<InsertValueInst>(I2)->idx_begin()[i])
|
if (const FenceInst *FI = dyn_cast<FenceInst>(I1))
|
||||||
return false;
|
return FI->getOrdering() == cast<FenceInst>(I2)->getOrdering() &&
|
||||||
return true;
|
FI->getSynchScope() == cast<FenceInst>(I2)->getSynchScope();
|
||||||
}
|
if (const AtomicCmpXchgInst *CXI = dyn_cast<AtomicCmpXchgInst>(I1))
|
||||||
if (const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(I1)) {
|
return CXI->isVolatile() == cast<AtomicCmpXchgInst>(I2)->isVolatile() &&
|
||||||
if (EVI->getNumIndices() != cast<ExtractValueInst>(I2)->getNumIndices())
|
CXI->getOrdering() == cast<AtomicCmpXchgInst>(I2)->getOrdering() &&
|
||||||
return false;
|
CXI->getSynchScope() == cast<AtomicCmpXchgInst>(I2)->getSynchScope();
|
||||||
for (unsigned i = 0, e = EVI->getNumIndices(); i != e; ++i)
|
if (const AtomicRMWInst *RMWI = dyn_cast<AtomicRMWInst>(I1))
|
||||||
if (EVI->idx_begin()[i] != cast<ExtractValueInst>(I2)->idx_begin()[i])
|
return RMWI->getOperation() == cast<AtomicRMWInst>(I2)->getOperation() &&
|
||||||
return false;
|
RMWI->isVolatile() == cast<AtomicRMWInst>(I2)->isVolatile() &&
|
||||||
return true;
|
RMWI->getOrdering() == cast<AtomicRMWInst>(I2)->getOrdering() &&
|
||||||
}
|
RMWI->getSynchScope() == cast<AtomicRMWInst>(I2)->getSynchScope();
|
||||||
|
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
@ -115,6 +115,76 @@ static bool LowerAtomicIntrinsic(IntrinsicInst *II) {
|
|||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
bool LowerAtomicCmpXchgInst(AtomicCmpXchgInst *CXI) {
|
||||||
|
IRBuilder<> Builder(CXI->getParent(), CXI);
|
||||||
|
Value *Ptr = CXI->getPointerOperand();
|
||||||
|
Value *Cmp = CXI->getCompareOperand();
|
||||||
|
Value *Val = CXI->getNewValOperand();
|
||||||
|
|
||||||
|
LoadInst *Orig = Builder.CreateLoad(Ptr);
|
||||||
|
Value *Equal = Builder.CreateICmpEQ(Orig, Cmp);
|
||||||
|
Value *Res = Builder.CreateSelect(Equal, Val, Orig);
|
||||||
|
Builder.CreateStore(Res, Ptr);
|
||||||
|
|
||||||
|
CXI->replaceAllUsesWith(Orig);
|
||||||
|
CXI->eraseFromParent();
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
bool LowerAtomicRMWInst(AtomicRMWInst *RMWI) {
|
||||||
|
IRBuilder<> Builder(RMWI->getParent(), RMWI);
|
||||||
|
Value *Ptr = RMWI->getPointerOperand();
|
||||||
|
Value *Val = RMWI->getValOperand();
|
||||||
|
|
||||||
|
LoadInst *Orig = Builder.CreateLoad(Ptr);
|
||||||
|
Value *Res = NULL;
|
||||||
|
|
||||||
|
switch (RMWI->getOperation()) {
|
||||||
|
default: llvm_unreachable("Unexpected RMW operation");
|
||||||
|
case AtomicRMWInst::Xchg:
|
||||||
|
Res = Val;
|
||||||
|
break;
|
||||||
|
case AtomicRMWInst::Add:
|
||||||
|
Res = Builder.CreateAdd(Orig, Val);
|
||||||
|
break;
|
||||||
|
case AtomicRMWInst::Sub:
|
||||||
|
Res = Builder.CreateSub(Orig, Val);
|
||||||
|
break;
|
||||||
|
case AtomicRMWInst::And:
|
||||||
|
Res = Builder.CreateAnd(Orig, Val);
|
||||||
|
break;
|
||||||
|
case AtomicRMWInst::Nand:
|
||||||
|
Res = Builder.CreateNot(Builder.CreateAnd(Orig, Val));
|
||||||
|
break;
|
||||||
|
case AtomicRMWInst::Or:
|
||||||
|
Res = Builder.CreateOr(Orig, Val);
|
||||||
|
break;
|
||||||
|
case AtomicRMWInst::Xor:
|
||||||
|
Res = Builder.CreateXor(Orig, Val);
|
||||||
|
break;
|
||||||
|
case AtomicRMWInst::Max:
|
||||||
|
Res = Builder.CreateSelect(Builder.CreateICmpSLT(Orig, Val),
|
||||||
|
Val, Orig);
|
||||||
|
break;
|
||||||
|
case AtomicRMWInst::Min:
|
||||||
|
Res = Builder.CreateSelect(Builder.CreateICmpSLT(Orig, Val),
|
||||||
|
Orig, Val);
|
||||||
|
break;
|
||||||
|
case AtomicRMWInst::UMax:
|
||||||
|
Res = Builder.CreateSelect(Builder.CreateICmpULT(Orig, Val),
|
||||||
|
Val, Orig);
|
||||||
|
break;
|
||||||
|
case AtomicRMWInst::UMin:
|
||||||
|
Res = Builder.CreateSelect(Builder.CreateICmpULT(Orig, Val),
|
||||||
|
Orig, Val);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
Builder.CreateStore(Res, Ptr);
|
||||||
|
RMWI->replaceAllUsesWith(Orig);
|
||||||
|
RMWI->eraseFromParent();
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
static bool LowerFenceInst(FenceInst *FI) {
|
static bool LowerFenceInst(FenceInst *FI) {
|
||||||
FI->eraseFromParent();
|
FI->eraseFromParent();
|
||||||
return true;
|
return true;
|
||||||
@ -134,6 +204,10 @@ namespace {
|
|||||||
Changed |= LowerAtomicIntrinsic(II);
|
Changed |= LowerAtomicIntrinsic(II);
|
||||||
else if (FenceInst *FI = dyn_cast<FenceInst>(Inst))
|
else if (FenceInst *FI = dyn_cast<FenceInst>(Inst))
|
||||||
Changed |= LowerFenceInst(FI);
|
Changed |= LowerFenceInst(FI);
|
||||||
|
else if (AtomicCmpXchgInst *CXI = dyn_cast<AtomicCmpXchgInst>(Inst))
|
||||||
|
Changed |= LowerAtomicCmpXchgInst(CXI);
|
||||||
|
else if (AtomicRMWInst *RMWI = dyn_cast<AtomicRMWInst>(Inst))
|
||||||
|
Changed |= LowerAtomicRMWInst(RMWI);
|
||||||
}
|
}
|
||||||
return Changed;
|
return Changed;
|
||||||
}
|
}
|
||||||
|
@ -216,6 +216,15 @@ bool Instruction::isIdenticalToWhenDefined(const Instruction *I) const {
|
|||||||
if (const FenceInst *FI = dyn_cast<FenceInst>(this))
|
if (const FenceInst *FI = dyn_cast<FenceInst>(this))
|
||||||
return FI->getOrdering() == cast<FenceInst>(FI)->getOrdering() &&
|
return FI->getOrdering() == cast<FenceInst>(FI)->getOrdering() &&
|
||||||
FI->getSynchScope() == cast<FenceInst>(FI)->getSynchScope();
|
FI->getSynchScope() == cast<FenceInst>(FI)->getSynchScope();
|
||||||
|
if (const AtomicCmpXchgInst *CXI = dyn_cast<AtomicCmpXchgInst>(this))
|
||||||
|
return CXI->isVolatile() == cast<AtomicCmpXchgInst>(I)->isVolatile() &&
|
||||||
|
CXI->getOrdering() == cast<AtomicCmpXchgInst>(I)->getOrdering() &&
|
||||||
|
CXI->getSynchScope() == cast<AtomicCmpXchgInst>(I)->getSynchScope();
|
||||||
|
if (const AtomicRMWInst *RMWI = dyn_cast<AtomicRMWInst>(this))
|
||||||
|
return RMWI->getOperation() == cast<AtomicRMWInst>(I)->getOperation() &&
|
||||||
|
RMWI->isVolatile() == cast<AtomicRMWInst>(I)->isVolatile() &&
|
||||||
|
RMWI->getOrdering() == cast<AtomicRMWInst>(I)->getOrdering() &&
|
||||||
|
RMWI->getSynchScope() == cast<AtomicRMWInst>(I)->getSynchScope();
|
||||||
|
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
@ -257,8 +266,17 @@ bool Instruction::isSameOperationAs(const Instruction *I) const {
|
|||||||
if (const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(this))
|
if (const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(this))
|
||||||
return EVI->getIndices() == cast<ExtractValueInst>(I)->getIndices();
|
return EVI->getIndices() == cast<ExtractValueInst>(I)->getIndices();
|
||||||
if (const FenceInst *FI = dyn_cast<FenceInst>(this))
|
if (const FenceInst *FI = dyn_cast<FenceInst>(this))
|
||||||
return FI->getOrdering() == cast<FenceInst>(FI)->getOrdering() &&
|
return FI->getOrdering() == cast<FenceInst>(I)->getOrdering() &&
|
||||||
FI->getSynchScope() == cast<FenceInst>(FI)->getSynchScope();
|
FI->getSynchScope() == cast<FenceInst>(I)->getSynchScope();
|
||||||
|
if (const AtomicCmpXchgInst *CXI = dyn_cast<AtomicCmpXchgInst>(this))
|
||||||
|
return CXI->isVolatile() == cast<AtomicCmpXchgInst>(I)->isVolatile() &&
|
||||||
|
CXI->getOrdering() == cast<AtomicCmpXchgInst>(I)->getOrdering() &&
|
||||||
|
CXI->getSynchScope() == cast<AtomicCmpXchgInst>(I)->getSynchScope();
|
||||||
|
if (const AtomicRMWInst *RMWI = dyn_cast<AtomicRMWInst>(this))
|
||||||
|
return RMWI->getOperation() == cast<AtomicRMWInst>(I)->getOperation() &&
|
||||||
|
RMWI->isVolatile() == cast<AtomicRMWInst>(I)->isVolatile() &&
|
||||||
|
RMWI->getOrdering() == cast<AtomicRMWInst>(I)->getOrdering() &&
|
||||||
|
RMWI->getSynchScope() == cast<AtomicRMWInst>(I)->getSynchScope();
|
||||||
|
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
@ -292,6 +310,8 @@ bool Instruction::mayReadFromMemory() const {
|
|||||||
case Instruction::VAArg:
|
case Instruction::VAArg:
|
||||||
case Instruction::Load:
|
case Instruction::Load:
|
||||||
case Instruction::Fence: // FIXME: refine definition of mayReadFromMemory
|
case Instruction::Fence: // FIXME: refine definition of mayReadFromMemory
|
||||||
|
case Instruction::AtomicCmpXchg:
|
||||||
|
case Instruction::AtomicRMW:
|
||||||
return true;
|
return true;
|
||||||
case Instruction::Call:
|
case Instruction::Call:
|
||||||
return !cast<CallInst>(this)->doesNotAccessMemory();
|
return !cast<CallInst>(this)->doesNotAccessMemory();
|
||||||
@ -310,6 +330,8 @@ bool Instruction::mayWriteToMemory() const {
|
|||||||
case Instruction::Fence: // FIXME: refine definition of mayWriteToMemory
|
case Instruction::Fence: // FIXME: refine definition of mayWriteToMemory
|
||||||
case Instruction::Store:
|
case Instruction::Store:
|
||||||
case Instruction::VAArg:
|
case Instruction::VAArg:
|
||||||
|
case Instruction::AtomicCmpXchg:
|
||||||
|
case Instruction::AtomicRMW:
|
||||||
return true;
|
return true;
|
||||||
case Instruction::Call:
|
case Instruction::Call:
|
||||||
return !cast<CallInst>(this)->onlyReadsMemory();
|
return !cast<CallInst>(this)->onlyReadsMemory();
|
||||||
|
Loading…
Reference in New Issue
Block a user